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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Control > Branching (e.g., Delayed Branch, Loop Control, Branch Predict, Interrupt) > Conditional Branching > Prefetching A Branch Target (i.e., Look Ahead) > Branch Target Buffer Branch Target BufferBranch Target Buffer patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236080 - Reducing the fetch time of target instructions of a predicted taken branch instruction A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of ... 10/05/06 - 20060224870 - Information processing device The present invention is defined in that an information processing device which reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing comprises: an instruction reading request portion which assigns a read address to the instruction store portion; an instruction buffering portion including a plurality of ... 09/28/06 - 20060218385 - Branch target address cache storing two or more branch target addresses per index A Branch Target Address Cache (BTAC) stores at least two branch target addresses in each cache line. The BTAC is indexed by a truncated branch instruction address. An offset obtained from a branch prediction offset table determines which of the branch target addresses is taken as the predicted branch target ... 09/07/06 - 20060200655 - Forward looking branch target address caching A pipelined processor comprises an instruction cache (iCache), a branch target address cache (BTAC), and processing stages, including a stage to fetch from the iCache and the BTAC. To compensate for the number of cycles needed to fetch a branch target address from the BTAC, the fetch from the BTAC ... 08/03/06 - 20060174096 - Methods and systems for storing branch information in an address table of a processor Methods and systems for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and ... 05/04/06 - 20060095745 - Processes, circuits, devices, and systems for branch prediction and other processor improvements A processor (1700) including a pipeline (1710, 1740) having a fetch pipeline (1710) with branch prediction circuitry (1840) to supply respective predicted taken target addresses for branch instructions, an execution pipeline (1740) with a branch execution circuit (1870), and storage elements (in 1860) and control logic (2350) operable to establish ... 05/04/06 - 20060095744 - Memory control circuit and microprocessor system A memory control circuit for providing a small-circuit-size memory control circuit capable of reducing a branch penalty during the execution of a branch instruction in a CPU. A branch-destination buffer caches a branch-destination instruction and a branch-destination-instruction address determined by a branch instruction executed by the CPU. When the CPU ... 02/16/06 - 20060036836 - Block-based branch target buffer The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction for a “block” of instruction memory. The block of instruction ... 01/12/06 - 20060010310 - Apparatus and method for handling btac branches that wrap across instruction cache lines A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines. When an instruction cache fetch address of a first cache line containing the first part of the branch instruction hits in ... 12/15/05 - 20050278516 - Predicted return address selection upon matching target in branch history table with entries in return address stack An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history). The information processing apparatus, in order to process an instruction sequence that includes a subroutine at a high speed, is further equipped with a ... 11/17/05 - 20050257035 - Linked instruction buffering of basic blocks for asynchronous predicted taken branches A method and apparatus for providing the capability to create a dynamic based buffer structure that takes an instruction addresses organized instruction cache and through the interaction of an asynchronous branch target buffer (BTB) and branch history table (BHT) forms a series of instructions that resembles a trace cache in ... 09/29/05 - 20050216713 - Instruction text controlled selectively stated branches for prediction via a branch target buffer Disclosed is a method and apparatus providing the capability to prevent particular branches from being written into the BTB, thereby making them non-predictable. By making certain branches only detectable at decode time frame, branch prediction can completely run asynchronous of decode. By allowing branch prediction logic to cover as wide ... 09/22/05 - 20050210224 - Processor including fallback branch prediction mechanism for far jump and far call instructions A method and apparatus are provided for processing far jump-call branch instructions within a processor in a manner which reduces the number of stalls of the processor pipeline. The processor includes an apparatus, for providing a fallback far jump-call speculative target address that corresponds to a current far jump-call branch ... 09/15/05 - 20050204120 - Effective delayed, minimized switching, btb write via recent entry queue that has the ability to delay decode Disclosed is a method and apparatus providing the capability to supplement a branch target buffer (BTB) with a recent entry queue. A recent entry queue prevents unnecessary removal of valuable BTB data of multiple entries for another entry. Additional, the recent entry queue detects when the latency of the BTB's ... 09/08/05 - 20050198481 - Apparatus and method for densely packing a branch instruction predicted by a branch target address cache and associated target instructions into a byte-wide instruction buffer A branch control apparatus in a microprocessor. A register receives a first cache line containing a branch instruction from an instruction cache in response to a fetch address. The fetch address hits in a BTAC that provides a target address of the branch instruction. The BTAC also provides an offset ... 06/16/05 - 20050132173 - Method and apparatus for allocating entries in a branch target buffer A method (200) and apparatus (100) for allocating entries in a branch target buffer (BTB) (144) in a pipelined data processing system includes: sequentially fetching instructions; determining that one of the instructions is a branch instruction (210, 215, 220); decoding the branch instruction to determine a branch target address; determining ... ### FreshPatents.com Support |