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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Control > Branching (e.g., Delayed Branch, Loop Control, Branch Predict, Interrupt) > Conditional Branching > Prefetching A Branch Target (i.e., Look Ahead) Prefetching A Branch Target (i.e., Look Ahead)Prefetching A Branch Target (i.e., Look Ahead) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/17/05 - 20050257034 - Branch target aware instruction prefetching technique Inspecting a currently fetched instruction group and determining branching behavior of the currently fetched instruction group, allows for intelligent instruction prefetching. A currently fetched instruction group is predecoded and, assuming the currently fetch instruction group includes a branch type instruction, a branch target is characterized in relation to a fetch ... 10/06/05 - 20050223202 - Branch prediction in a pipelined processor A new branch notification processor instruction may be added to a pipelined processor with static branch prediction. The instruction may be used to instruct the processor to fetch the instruction at the branch's target. ... 09/08/05 - 20050198480 - Apparatus and method of controlling instruction fetch An instruction control apparatus, and method, used with a device including a cache memory, a lower memory, an instruction fetch device issuing an instruction fetch request for a target of a first branch instruction to the cache memory, and an instruction control device processing a instruction sequence stored in the ... 09/08/05 - 20050198479 - Apparatus and method for handling btac branches that wrap across instruction cache lines A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines. When an instruction cache fetch address of a first cache line containing the first part of the branch instruction hits in ... ### FreshPatents.com Support |