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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Control > Branching (e.g., Delayed Branch, Loop Control, Branch Predict, Interrupt) > Conditional Branching Conditional BranchingConditional Branching patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/21/06 - 20060212690 - System and method for processing complex computer instructions A system and method for handling complex instructions are provided. The process includes generating a jump instruction from an address which may be embedded in a computer instruction and selecting the original instruction if it was not complex or the jump instruction if it was. ... 08/03/06 - 20060174095 - Branch encoding before instruction cache write Method, system and computer program product for determining the targets of branches in a data processing system. A method for determining the target of a branch in a data processing system includes performing at least one pre-calculation relating to determining the target of the branch prior to Writing the branch ... 07/13/06 - 20060155976 - Processor, microcomputer and method for controlling program of microcomputer A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgement instruction in the special task, ... 07/13/06 - 20060155975 - Method and apparatus for processing conditonal branch instructions In the programming of a microcontroller (100) carried out in at least one machine-dependent assembly language in which the assembler commands, with the exception of conditional program branches, are executable essentially independently of data,—in case of a fulfilled branch condition, for example, at least one fulfilled status flag, at least ... 07/06/06 - 20060149943 - System and method for simulating hardware interrupts A system and method is provided to simulate hardware interrupts by inserting instructions into a stream of instructions where a “no operation” (or NOOP) instruction would normally be inserted. The instruction is inserted is a conditional branch instruction, called a BISLED, that branches if there is external data in a ... 07/06/06 - 20060149942 - Microcontroller and assigned method for processing the programming of the micro-con- troller In order to further develop a microcontroller (100) the programming of which is carried out in at least one machine-dependent assembler language in which the assembler commands, with the exception of conditional program jumps or branches, can be executed in essence independently of data, together with a method for processing ... 12/29/05 - 20050289330 - Branch control method and information processor An object of the present invention is to provide a branch control method and an information processor in which when an instruction that can be processed in a delayed slot is present, a delayed branch is implemented to eliminate a branch hazard, and even when there is no such an ... 12/29/05 - 20050289329 - Conditional instruction for a single instruction, multiple data execution engine According to some embodiments, a conditional Single Instruction, Multiple Data instruction is provided. For example, a first conditional instruction may be received at an n-channel SIMD execution engine. The first conditional instruction may be evaluated based on multiple channels of associated data, and the result of the evaluation may be ... 12/15/05 - 20050278515 - Information processing apparatus, microcomputer, and electronic computer An information processing apparatus performing pipeline control includes a first fetch cue fetching a non-branch location instruction, a second fetch cue fetching a branch location instruction, a fetch circuit which carries out arithmetic of a fetch address, fetch it to the first fetch cue or the second fetch cue, and ... 12/15/05 - 20050278514 - Condition bits for controlling branch processing A processing pipeline with a plurality of pipeline stages is described, with the processing pipeline comprising a front end and a back end. The processing pipeline's front end comprises an array for storing at least two condition bits, said condition bits being adapted for indicating respective conditions. The front end ... 11/17/05 - 20050257032 - Accessing a test condition A method and system of executing computer instructions is described. Each instruction defines first and second operands and an operation to be carried out on said operands. Each instruction also contains an address field of a predetermined bit length which identifies a test register holding a plurality of test bits ... 10/06/05 - 20050223198 - Optimized processors and instruction alignment Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported ... 09/29/05 - 20050216712 - Compare and branch mechanism A data processing system is provided that includes an instruction decoder 20 responsive to a compare and branch instruction CHKA.X that performs a comparison between first and second values stored in first and second registers Rn, Rm respectively. A target branch address is determined from a pre-programmed stored value and ... 09/08/05 - 20050198478 - Setting condition values in a computer A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation and contains a condition setting indicator settable independently of the operation. The status of the condition setting indicator determines whether ... 07/07/05 - 20050149706 - Efficient link and fall-through address calculation A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address of a first set of bytes including a branch instruction and a second address of a second set of bytes contiguous to ... ### FreshPatents.com Support |