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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Control > Branching (e.g., Delayed Branch, Loop Control, Branch Predict, Interrupt) Branching (e.g., Delayed Branch, Loop Control, Branch Predict, Interrupt)Branching (e.g., Delayed Branch, Loop Control, Branch Predict, Interrupt) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.07/27/06 - 20060168431 - Method and apparatus for jump delay slot control in a pipelined processor An improved method and apparatus for implementing instructions in a pipelined central processing unit (CPU) or user-customizable microprocessor. In a first aspect of the invention, an improved method of controlling branching and the execution of instructions within the pipeline is disclosed. In one embodiment, the method comprises defining three discrete ... 07/20/06 - 20060161762 - Method and logical apparatus for managing processing system resource use for speculative execution A method and logical apparatus for managing processing system resource use for speculative execution reduces the power and performance burden associated with inefficient speculative execution of program instructions. A measure of the efficiency of speculative execution is used to reduce resources allocated to a thread while the speculation efficiency is ... 05/11/06 - 20060101255 - Method and apparatus for clearing hazards using jump instructions A method and apparatus for overlaying hazard clearing with a jump instruction within a pipeline microprocessor is described. The apparatus includes hazard logic to detect when a jump instruction specifies that hazards are to be cleared as part of a jump operation. If hazards are to be cleared, the hazard ... 11/10/05 - 20050251667 - Systems and methods for task migration Methods and systems are provided whereby, in one aspect, pointers to address locations of instructions, static data and dynamically-created data are stored such that the instructions, static data and dynamically-created data can be moved to a different memory or processor without changing the values of the pointers. ... 09/29/05 - 20050216711 - Null exception handling A processor 6 is provided with an instruction decoder 18 which is responsive to memory access instructions to determine whether the base register value being used matches a null value and if such a match occurs then branches to a null value exception handler. ... 06/09/05 - 20050125644 - Specifying different type generalized event and action pair in a processor A processor with a generalized eventpoint architecture, which is scalable for use in a very long instruction word (VLIW) array processor, such as the manifold array (ManArray) processor is described. In one aspect, generalized processor event (p-event) detection facilities are provided by use of compares to check if an instruction ... ### FreshPatents.com Support |