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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Control > Context Preserving (e.g., Context Swapping, Checkpointing, Register Windowing Context Preserving (e.g., Context Swapping, Checkpointing, Register WindowingContext Preserving (e.g., Context Swapping, Checkpointing, Register Windowing patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/12/06 - 20060230258 - Multi-thread processor and method for operating such a processor A multithread processor with synchronization of a command flow, with an associated data flow and with generation of a memory-triggered context switch signal comprises a synchronization device configured, when receiving a load cycle indicator flag with a positive logic signal level from a memory read access unit, to load and ... 10/05/06 - 20060224869 - Combination of forwarding/bypass network with history file An apparatus, a method, and a processor are provided for recovering the correct state of processor instructions in a processor. This apparatus contains a pipeline of latches, a register file, and a replay loop. The replay loop repairs incorrect results and inserts the repaired results back into the pipeline. A ... 09/21/06 - 20060212689 - Method and apparatus for simultaneous speculative threading One embodiment of the present invention provides a system which performs simultaneous speculative threading. The system starts by executing instructions in normal execution mode using a first thread. Upon encountering a data-dependent stall condition, the first thread generates an architectural checkpoint and commences execution of instructions in execute-ahead mode. During ... 09/21/06 - 20060212688 - Generation of multiple checkpoints in a processor that supports speculative execution One embodiment of the present invention provides a system which creates multiple checkpoints in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during an instruction which causes a ... 09/21/06 - 20060212687 - Dual thread processor A pipeline processor architecture, processor, and methods are provided. In one implementation, a processor is provided that includes an instruction fetch unit operable to fetch instructions associated with a plurality of processor threads, a decoder responsive to the instruction fetch unit, issue logic responsive to the decoder, and a register ... 08/31/06 - 20060195684 - Reconfigurable data processing device and method A reconfigurable data processing device equipped with a plurality of data processing units controls timing of switching contents of data processing executed by each of the plurality of data processing units for each of a plurality of data processing operations. ... 08/31/06 - 20060195683 - Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts A multiprocessing system is disclosed. The system includes a multithreading microprocessor including a plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread. The microprocessor also includes a shared privileged resource, shared by the plurality of TCs rather than being ... 08/10/06 - 20060179291 - Multithread processor and method for operating a multithread processor A multithread processor for the data processing of a plurality of threads, each being provided with a dedicated context, comprises a switching table. The switching table receives at least one of an internal exception of a specific context for updating the specific context and for switching from the specific context ... 08/10/06 - 20060179290 - System and method for creating precise exceptions A method for creating precise exceptions including checkpointing an exception causing instruction. The checkpointing results in a current checkpointed state. The current checkpointed state is locked. It is determined if any of a plurality of registers require restoration to the current checkpointed state. One or more of the registers are ... 07/27/06 - 20060168430 - Apparatus and method for concealing switch latency An multi-threading processor is provided. The multi-threading processor includes a front end module, an execution module coupled to the front end module, and a state module coupled to both the front end module and the execution module. The processor also includes a switch logic module, which is coupled to the ... 07/27/06 - 20060168429 - Deterministic microcontroller with configurable input/output interface A deterministic microcontroller includes a plurality of blocks of cache memories formed on the same integrated circuit as the microprocessor unit. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers. A context manager controls the selection of the hardware registers ... 07/27/06 - 20060168428 - Method of providing microcontroller context management A method of operating a deterministic microcontroller is disclosed in which the microcontroller is switchable to various contexts. A plurality of sets of hardware registers is provided. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers. A context manager controls ... 07/27/06 - 20060168427 - Deterministic microcontroller with context manager A deterministic microprocessor is disclosed in which a plurality of sets of hardware registers is provided. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers. A context manager controls the selection of the hardware registers such that contexts are changed ... 07/13/06 - 20060155973 - Multithreaded hardware systems and methods Multithreaded hardware systems and methods are disclosed. One embodiment of a system may comprise a multithreaded processor comprising a register file having N hardware threads, where N is an integer greater than or equal to one, and an offline storage structure having M hardware threads, where M is an integer ... 07/13/06 - 20060155972 - Method in pipelined data processing A method in a processor is presented, in which data is processed in a pipelined manner, the data being included in a plurality of contexts, comprising a first (3), in addition to which a plurality of operations is adapted to be executed on the contexts. The method comprises executing an ... 07/06/06 - 20060149940 - Implementation to save and restore processor registers on a context switch A method and apparatus for enabling a processor to perform a save and restore on a context switch incrementally and on demand. In one embodiment, when OS switches to a new process, the processor saves only those registers that have been modified in the current process. The processor may not ... 05/11/06 - 20060101254 - Start transactional execution (ste) instruction to support transactional program execution One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the ... 05/11/06 - 20060101253 - Computing machine with redundancy and related systems and methods According to an embodiment of the invention, a computing machine comprises a pipeline accelerator, a host processor coupled to the pipeline accelerator, and a redundant processor, a redundant pipeline unit, or both, coupled to the host processor and to the pipeline accelerator. The computing machine may also include a system-restore ... 05/11/06 - 20060101252 - Information processing apparatus and context switching method An information processing apparatus which, when executing a plurality of predetermined units of processing, executes the predetermined units of processing in parallel by a processor by switching between contexts associated with the respective predetermined units. The processing apparatus comprises a plurality of register banks that respectively store the contexts associated ... 05/04/06 - 20060095743 - Vliw processor with copy register file A compute program is executed in a VLIW processor, which contains a plurality of functional units and a plurality of register files that are each coupled to a respective subset of the functional units. When a first instruction is executed that results in writing of a result to a register ... 02/02/06 - 20060026407 - Delegating tasks between multiple processor cores An electronic device comprising a first processor and a second processor, the second processor coupled to the first processor and adapted to receive an address from the first processor, to pause execution of a first thread at a switch point, and to use the address to retrieve and execute a ... 02/02/06 - 20060026406 - Unprivileged context management Embodiments of the present invention provide full benefit of the cover instruction provided by the Intel IA-64 architecture to code running at less than highest privilege level. In one embodiment of the present invention, prior to execution of a cover instruction by non-privileged code, the code obtains and stores the ... 01/12/06 - 20060010308 - Microprocessor A microprocessor executes programs in a pipeline architecture that includes a task register management unit that switches a value of a task register to second register information that is used when a second task is executed after the execution of a first task is completed, if a switch instruction to ... 12/29/05 - 20050289328 - Reconfigurable processor and semiconductor device A reconfigurable processor that finely controls operation without exerting an influence upon other functions. Register groups are connected to input ports of ALUs via selectors. Data inputted to an ALU is held in a register selected by a selector under the control of a sequencer. For example, it is assumed ... 12/15/05 - 20050278513 - Systems and methods of dynamic branch prediction in a microprocessor A hybrid branch prediction scheme for a multi-stage pipelined microprocessor that combines features of static and dynamic branch prediction to reduce complexity and enhance performance over conventional branch prediction techniques. Prior to microprocessor deployment, a branch prediction table is populated using static branch prediction techniques by executing instructions analogous to ... 12/15/05 - 20050278512 - Context switching devices, systems and methods A data processing device includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return ... 11/10/05 - 20050251666 - Method and apparatus for avoiding raw hazards in an execute-ahead processor One embodiment of the present invention provides a system that avoids read-after-write (RAW) hazards while speculatively executing instructions on a processor. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering a stall condition during execution of an instruction, the ... 11/10/05 - 20050251665 - Method and apparatus for avoiding war hazards in an execute-ahead processor One embodiment of the present invention provides a system that avoids write-after-read (WAR) hazards while speculatively executing instructions on a processor. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, ... 11/10/05 - 20050251664 - Method and apparatus for avoiding waw hazards in an execute-ahead processor One embodiment of the present invention provides a system that avoids write-after-write (WAW) hazards while speculatively executing instructions. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates ... 11/10/05 - 20050251663 - Computer architechture including implemented and unimplemented registers A computer architecture includes a predetermined number of architected registers. The architected registers include a plurality of implemented registers and a plurality of unimplemented registers. ... 11/10/05 - 20050251662 - Secondary register file mechanism for virtual multithreading Method, apparatus and system embodiments provide one or more secondary register files to store register values for inactive virtual software threads in a virtual multithreading environment. A separate secondary register file may maintain logical register values for each inactive virtual thread. ... 09/29/05 - 20050216710 - Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing data including programming engines that support multiple contexts arranged to provide a functional ... 09/29/05 - 20050216709 - Microprocessor that carries out context switching with ringed shift register A microprocessor includes a first ringed shift register having a plurality of registers storing a plurality of context information respectively, the registers being connected in a loop, an instruction decoder transmitting the context information to a reference register in the first ringed shift register, an instruction execution unit exchanging the ... 09/29/05 - 20050216708 - Processor for performing context switching, a method for performing context switching, a computer program for perform context switching A processor for performing context switching, including: (a) a register unit configured to include a primary register used in program execution by the processor and a secondary register having a same structure as the primary register; (b) a data storage unit configured to be used as a data storage area ... 09/08/05 - 20050198477 - Synchronous network traffic processor A synchronous network traffic processor that synchronously processes, analyzes and generates data for high-speed network protocols, on a wire-speed, word-by-word basis. The synchronous network processor is protocol independent and may be programmed to convert protocols on the fly. An embodiment of the synchronous network processor described has a low gate ... 09/08/05 - 20050198476 - Parallel multithread processor (pmt) with split contexts The present invention relates to a parallel multithread processor (1) with split contexts, with M parallel-connected standard processor root units (2) being provided for instruction execution of program instructions for different threads (T), and with N context memories (3) being provided, which each temporarily store a current state of a ... 09/08/05 - 20050198475 - Thread selection unit and method to fairly allocate processor cycles in a block multithreaded processor A thread selection unit for a block multi-threaded processor includes a priority thread selector and an execution thread selector. The priority thread selector uses a maxtime register for each active thread to limit the time an active thread can be the priority thread. The execution thread selector is configured to ... 09/01/05 - 20050193186 - Heterogeneous parallel multithread processor (hpmt) with shared contexts The invention relates to a heterogeneous parallel multithread processor (1) with shared contexts which has a plurality (M) of parallel-connected standard processor root unit types (2p; pε[1, . . . , M]), where each respective standard processor root unit type (2p) has at least one or more (K) parallel-connected standard ... 08/04/05 - 20050172108 - Device and method of switching registers to be accessed by changing operating modes in a processor A device and method of switching registers to be accessed by changing operating modes in a processor. The processor has a plurality of operating modes. The device has a register address decoder, at least one first register, a plurality of second registers and a selection device. The register address decoder ... 07/21/05 - 20050160254 - Multithread processor architecture for triggered thread switching without any clock cycle loss, without any switching program instruction, and without extending the program instruction format A multithread processor based on the inventive architecture is a clocked multithread processor (1) for data processing of N threads by means of a standard processor root unit (2), wherein a thread Tj which is to be processed at any given time by the standard processor root unit (2) can ... 07/14/05 - 20050154866 - Systems and methods for executing across at least one memory barrier employing speculative fills Multi-processor systems and methods are disclosed. One embodiment may comprise a processor having a processor pipeline that executes program instructions across at least one memory barrier with data from speculative data fills that are provided in response to source requests, and a log that retains executed load instruction entries associated ... 07/14/05 - 20050154865 - Multi-processor systems and methods for backup for non-coherent speculative fills Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source request, and a backup system that retains information associated with a previous ... 06/23/05 - 20050138340 - Method and apparatus to reduce spill and fill overhead in a processor with a register backing store A method and apparatus for selectively storing a register stack onto a register stack backing store is disclosed. In one embodiment, a non-exclusive boundary is determined enclosing registers that were actually used (e.g. written to) by a function. The description of that boundary is saved, and only the contents of ... 06/09/05 - 20050125643 - Architecture for a processor complex of an arrayed pipelined processing engine A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store ... ### FreshPatents.com Support |