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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Control > Specialized Instruction Processing In Support Of Testing, Debugging, Emulation Specialized Instruction Processing In Support Of Testing, Debugging, EmulationSpecialized Instruction Processing In Support Of Testing, Debugging, Emulation patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/05/06 - 20060224868 - Branch tracing generator device for a microprocessor and microprocessor equipped with such a device A device for generating an address branch trace for a microcontroller unit, a microprocessor or a data processing unit having a set of instructions including at least one predicated instruction and at least one instruction of the expanded type, said device including: means for receiving a first signal representative of ... 09/28/06 - 20060218384 - Emulation pause and reset tracing of multiple sync points pointing to different addresses A method of tracing data processor activity includes trace data markers indicating initiation and termination of at least one trace function at a specified program counter address and emulation pause related markers indicating initiation and termination of an emulation halt state at a specified program counter. Each emulation pause related ... 09/14/06 - 20060206696 - Reconfigurable processor The present invention provides a reconfigurable processing apparatus enabling clusters to utilize a shared functional unit by using data and a validity signal received from the clusters by way of a network therebetween. In the reconfigurable processing apparatus comprising one or more clusters which are reconfigured based on configuration information, ... 08/31/06 - 20060195682 - Monitoring device with optimized buffer The invention concerns a monitoring device (18) integrated to a microprocessor chip (12) executing a series of instructions comprising: means (26) for producing simultaneously several types of monitoring messages of the microprocessor, a buffer (28) divided into several blocks (A, B, C, D, E) each of which is designed to ... 08/17/06 - 20060184777 - Method, apparatus and computer program product for identifying sources of performance events Event vectors are included in an instruction tracking structure of a processor to collect history for every instruction flowing through the processor. Such an event vector, by its nature, cannot be whole until the vector's corresponding instruction completes. However, some information for the event vector is collected earlier, i.e., as ... 08/17/06 - 20060184776 - Methods to randomly or pseudo-randomly, without bias, select instruction for performance analysis in a microprocessor A method for pseudo-randomly, without bias, selecting instructions for marking in a microprocessor. Responsive to reading an instruction from an instruction cache, an instruction tag associated with the instruction is compared against a pseudo-randomly generated value in a linear feedback shift register (LFSR). If the instruction tag matches the value ... 08/10/06 - 20060179289 - Intelligent smt thread hang detect taking into account shared resource contention/blocking Monitoring is performed to detect a hang condition. A timer is set to detect a hang based on a core hang limit. If a thread hangs for the duration of the core hang limit, then a core hang is detected. If the thread is performing an external memory transaction, then ... 07/13/06 - 20060155971 - Transmission of a digital message between a microprocessor monitoring circuit and an analysis tool The invention relates to a method for the transmission of digital messages by a monitoring circuit (18) which is integrated into a microprocessor (12), said method being performed during the execution of a series of instructions by the microprocessor. Moreover, at least one of said digital messages represents the detection ... 07/13/06 - 20060155970 - Monitoring a microprocessor programme by sending time-trackable messages The invention concerns a monitoring device (18′, 18″) integrated to the chip of a microprocessor (12) executing a series of instructions comprising message calculating means (36) for upon each execution of an instruction, producing a corresponding digital message; a buffer memory (34) for storing each message produced; and a plurality ... 04/06/06 - 20060075212 - Programmable logic analyzer data analyzing method A programmable logic analyzer data analyzing method includes the step of controlling a control circuit to fetch waveform data from the test sample and to store fetched waveform data in a memory, the step of controlling the control circuit to transmit the waveform data from the memory to a computer ... 03/23/06 - 20060064570 - Method and apparatus for automatically generating test data for code testing purposes One embodiment of the present invention provides a system that automatically generates test data for code testing purposes. During operation, the system receives code under test (CUT). The system then determines type information for one or more parameters for methods of the CUT. Next, the system automatically selects, based on ... 02/09/06 - 20060031662 - Processor implementing conditional execution and including a serial queue A processor is disclosed including trace and profile logic for gathering and producing data corresponding to events occurring during instruction execution. In one embodiment, the trace and profile logic includes a serial queue for serializing data corresponding to a plurality of “discontinuity instructions” grouped together for simultaneous execution. A “discontinuity ... 02/02/06 - 20060026405 - Identifying code for compilation A processor comprising fetch logic adapted to fetch a set of instructions from memory, the set comprising a subset of instructions. The processor further comprises decode logic coupled to the fetch logic and adapted to process the set of instructions, and a clock coupled to the decode logic. When processed, ... 02/02/06 - 20060026404 - Method and system to construct a data-flow analyzer for a bytecode verfier The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the first instruction to a decode logic ... 01/12/06 - 20060010307 - Latching processor state information A data processing apparatus and method is disclosed. The data processing apparatus comprises a processor unit operable to execute data processing instructions, a processor state register within the processor unit operable to store processor state information associated with a data processing instruction being executed by the processor unit and a ... 08/25/05 - 20050188186 - Obtaining execution path information in an instruction sampling system A method of linking control transfer information with sampling information for instructions executing in a processor which includes storing information relating to execution events, selecting an instruction for sampling, storing information relating to the instruction for sampling, freezing the information relating to execution events when the information relating to the ... 08/18/05 - 20050182919 - Secure processor arrangement A system and method for verifying the authenticity of instructions retrieved from a memory for execution by a processor. In one embodiment, an instruction monitor monitors execution parameters associated with the retrieved instruction and resets the system in response to an indication that an instruction is not authentic. ... 07/28/05 - 20050166039 - Programmable event driven yield mechanism which may activate other threads Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of ... 07/07/05 - 20050149705 - Pass through debug port on a high speed asynchronous link An example computer system includes a first bridge device that includes an interface controller. The interface controller combines debug information generated within the bridge device with a training pattern. The first bridge device is coupled to a second bridge device via a high-speed asynchronous interconnect. The first bridge device converts ... 06/30/05 - 20050144425 - Microprocessor arrangement and method for operating a microprocessor arrangement Microprocessor arrangement and a method for operating a microprocessor arrangement, where the microprocessor arrangement has an execution unit for controlling a program cycle and for processing arithmetic and logic operations, a working register which stores a result of an operation and which is coupled to a control element in the ... ### FreshPatents.com Support |