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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Control > Instruction Modification Based On Condition Instruction Modification Based On ConditionInstruction Modification Based On Condition patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236078 - System and method wherein conditional instructions unconditionally provide output A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides ... 10/05/06 - 20060224867 - Avoiding unnecessary processing of predicated instructions A processor comprising an instruction cache module adapted to store a plurality of instructions, the plurality of instructions comprising a group of instructions predicated on a conditional statement. The processor also comprises a branch prediction module coupled to the instruction cache module and adapted to predict an outcome of the ... 10/05/06 - 20060224866 - Selecting subroutine return mechanisms Following execution of a subroutine, a return instruction is executed having an address as an input operand thereto. This input operand is compared with one or more predetermined values to detect a match and the return instruction response is selected in dependence upon whether or not a match is detected. ... 09/21/06 - 20060212686 - Pipelined instruction processor with data bypassing An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction. A first register unit is coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline ... 09/07/06 - 20060200654 - Stop waiting for source operand when conditional instruction will not execute The delay of non-executing conditional instructions, that would otherwise be imposed while waiting for late operand data, is alleviated based on an early recognition that such instructions will not execute on the current pass through a pipeline processor. At an appropriate point prior to execution, a determination regarding the condition ... 09/07/06 - 20060200653 - Decoding predication instructions within a superscalar data processing system Within a multiple instruction pipeline data processing system which supports predication instructions, program instructions are initially decoded upon the assumption that they are predicated. A predication signal is generated within the instruction decoder stages when a predication instruction is detected. The presence or absence of this predication signal can then ... 08/17/06 - 20060184775 - Computer system with debug facility for debugging a processor capable of predicated execution A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in ... 08/17/06 - 20060184774 - Context-based operation reconfigurable instruction set processor and method of operation A reconfigurable context-based operation instruction set processor for use in a processing system capable of executing a first instruction set. The reconfigurable context-based operation instruction set processor comprises: 1) a reconfigurable data path comprising a plurality of reconfigurable functional blocks; and 2) a programmable finite state machine capable of controlling ... 08/10/06 - 20060179288 - Conditional instruction execution via emissary instruction for condition evaluation Hazard detection is simplified by converting a conditional instruction, operative to perform an operation if a condition is satisfied, into an emissary instruction operative to evaluate the condition and an unconditional base instruction operative to perform the operation. The emissary instruction is executed, while the base instruction is halted. The ... 08/03/06 - 20060174094 - Systems and methods for providing complementary operands to an alu Systems, methods and media for providing complementary operands to the arithmetic/logic unit of a processor are disclosed. A determination is made whether both a result of an instruction and a complement of that result are called for by a next instruction. If so, a value is input to a first ... 07/27/06 - 20060168426 - System and method for selectively controlling operations in lanes A computer system is disclosed capable of conditionally carrying out an operation defined in a computer instruction. The computer instruction is implemented on so-called packed operands, that is operands containing a plurality of packed objects in respective lanes. An operation defined in the computer instruction is conditionally carried out in ... 07/13/06 - 20060155969 - Reconfigurable, expandable semiconductor integrated circuit A semiconductor integrated circuit includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, a processing circuit including at least one of a fixed logic circuit configured to perform predetermined processing and a parameter-defined special-purpose hardware unit configured to change processing specifications according to parameter ... 07/13/06 - 20060155968 - Electronic computer, semiconductor integrated circuit, control method, program generation method, and program An application program is executed and is easily made reusable by dividing the application program into processing units, and by creating a logical circuit in the reconfigurable hardware by switching so as to improve the processing speed at low cost. The electronic computer comprises a processing device 70. The processing ... 05/11/06 - 20060101251 - System and method for simultaneously executing multiple conditional execution instruction groups A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a code block specified by the conditional execution instruction. In one embodiment, the processor includes multiple state machines simultaneously ... 05/11/06 - 20060101250 - Configurable computing machine and related systems and methods A computing machine includes programmable integrated circuits, a configuration registry, and a processor. The registry stores a file that defines a circuit having portions, and the processor is, in response to the file, operable to instantiate one of the circuit portions on one of the programmable integrated circuits. Consequently, by ... 05/11/06 - 20060101249 - Arrangements for adaptive response to latencies A response to the continuing trend of ever-increasing processor speeds and attendant increases in memory latencies. Broadly contemplated herein are braids and fibers, high-level programming constructs which facilitate the creation of programs that are partially ordered. These partial orders can be used to respond adaptively to memory latencies. It is ... 05/04/06 - 20060095742 - Method and apparatus for using predicates in a processing device A method of controlling an operation of a processing device that comprises at least a first and second predicate execution registers comprises predicating a first instruction on the first predicate execution register. A second instruction is predicated on the second predicate execution register. The first predicate execution register is set ... 04/27/06 - 20060090062 - Reconfigurable processor A processor includes a reconfigurable field of data processing cells. A register is provided where the register has a data stream memory designed to store a data stream and/or parts thereon. The register may be a RAM PAE. ... 02/16/06 - 20060036835 - Dsp processor architecture with write datapath word conditioning and analysis An improved digital signal processing (DSP) processor architecture is presented in which word conditioning (e.g., rounding, saturation, etc.) and analysis operations (e.g., block floating point analysis) are implemented in the write datapath to memory. By moving word conditioning operations from the critical path to the write datapath, the throughput of ... 02/02/06 - 20060026403 - Compare instruction A processor comprising fetch logic adapted to fetch instructions from memory and decode logic coupled to the fetch logic and adapted to decode the fetched instructions. If a bit in the decode logic is in a first state, a particular fetched instruction is skipped and a group of one or ... 02/02/06 - 20060026402 - Method and system of using a wide opcode other than prefix A method and related system of using a “WIDE” opcode as other than a prefix. At least some of the illustrative embodiments may be a method comprising fetching an opcode (the opcode used in at least some circumstances as a prefix to other opcodes), and determining whether the opcode is ... 02/02/06 - 20060026401 - Method and system to disable the wide prefix A method and related system to disable the “WIDE” prefix. At least some of the illustrative embodiments may be a method comprising disabling an ability of an opcode to act as a prefix for other opcodes. ... 02/02/06 - 20060026400 - Automatic operand load, modify and store A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in ... 01/26/06 - 20060020774 - Reconfigurable computing architecture for space applications A reconfigurable computer includes a reconfigurable processing element configured to process raw payload data in accordance with a configuration that is applied to the reconfigurable processing element. The reconfigurable computer further includes a multi-port communication device comprising a first port at which at least a portion of the raw payload ... 01/12/06 - 20060010306 - Reconfigurable operation apparatus A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs ... 01/05/06 - 20060004994 - Processor A processor executes a predetermined operation process by switching a connection structure between a plurality of arithmetic and logic unit modules. Each of the arithmetic and logic unit modules includes a plurality of arithmetic and logic units. The arithmetic and logic unit modules include a first arithmetic and logic unit ... 01/05/06 - 20060004993 - Processor and pipeline reconfiguration control method A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it ... 01/05/06 - 20060004992 - Reconfigurable circuit in which time division multiple processing is possible The reconfigurable circuit of the present invention in which time division multiple processing is possible has a pipeline structure with the number of stages of an integral multiple of a given number, and comprises a plurality of processor elements having a processing unit whose configuration is variable according to first ... 01/05/06 - 20060004991 - Semiconductor device A semiconductor device includes a configuration memory for storing configuration data, an arithmetic unit whose circuit configuration can be reconfigured in accordance with the configuration data, and a fixed value memory for storing fixed value data to be supplied to the arithmetic unit. Since the configuration data and fixed value ... 01/05/06 - 20060004990 - Distributed processing in a multiple processing unit environment Method and apparatus for performing distributed processing in a multi-processing unit environment. A first processing unit modifies a complex operation to provide an operational request packet comprising a corresponding simplex operation and remainder. The packet is communicated to a second processing unit which processes the packet to arrive at a ... 12/29/05 - 20050289327 - Reconfigurable processor and semiconductor device A reconfigurable processor in which an application can be switched more freely. A switching condition associating section associates output from a plurality of arithmetic and logic unit modules used as switching conditions for switching the operation of an arithmetic and logic unit group with a plurality of states indicative of ... 12/22/05 - 20050283592 - Dynamically controlling execution of operations within a multi-operation instruction Techniques are described for dynamically controlling the execution of operations within a multi-operation instruction, such as a very long instruction word (VLIW). A programmable processor fetches and executes a first instruction having an operation mask. Based on the operation mask, the processor selectively executes one or more operations within a ... 12/08/05 - 20050273581 - Programmable logic configuration for instruction extensions A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program comprising a set of computational instructions and at least one instruction extension. The programmable logic receives configuration information to configure the programmable logic for the ... 11/24/05 - 20050262331 - Controller and method for processing instructions A controller having a receiver for receiving an instruction, a comparator for comparing the received instruction to a predetermined wildcard instruction, the comparator providing a switch signal to a provider for providing a predetermined substitution instruction responsive to the predetermined wildcard instruction. Depending on the switch signal, the provider outputs ... 11/17/05 - 20050257031 - Field programmable gate array and microcontroller system-on-a-chip A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a ... 11/17/05 - 20050257030 - Programmable logic integrated circuit devices including dedicated processor components and hard-wired functional units A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) processor object (or at least a high-functionality functional unit) for performing or at least helping to perform tasks that it is unduly inefficient to implement in the more general-purpose programmable logic and/or ... 11/17/05 - 20050257029 - Adaptive processor architecture incorporating a field programmable gate array control element having at least one embedded microprocessor core A multi-adaptive processor element architecture incorporating a field programmable gate array (“FPGA”) control element having at least one embedded processor core and a pair of user FPGAs forming a user array is disclosed in conjunction with high volume dynamic random access memory (“DRAM”) and dual-ported static random access memory (“SRAM”) ... 11/10/05 - 20050251661 - Method and apparatus for handling transfer of guarded instructions in a computer system A method of transferring guard values and a computer system, such as a processor for digital signal processing, including a parallel set of execution units that utilizes the method. A master set of guard indicators is held in association with one of the execution units. If other execution units require ... 10/13/05 - 20050228976 - Microprocessor instruction execution method for exploiting parallelism A low overhead mechanism for supporting speculative execution and code compression in a Very Long Instruction Word (VLIW) microprocessor. Profitable speculations can be determined statically at compile time and a low overhead hardware recovery mechanism used that does not require compensation code. ... 10/06/05 - 20050223197 - Apparatus and method for dual data path processing A computer processor with control and data processing capabilities comprises a decode unit for decoding instructions. A data processing facility comprises a first data execution path including fixed operators and a second data execution path including at least configurable operators, the configurable operators having a plurality of predefined configurations, at ... 08/25/05 - 20050188185 - Method and apparatus for predicate implementation using selective conversion to micro-operations A method and apparatus for implementing predicated instructions using selective conversion to micro-operations is presented. In one embodiment, the predicated instructions may have both a prediction of the predicate value and an indication of the confidence value of that predicted predicate value generated. When the confidence value of the prediction ... 08/11/05 - 20050177707 - Method and apparatus for recoding instructions A method and apparatus for recoding one or more instruction sets. An expand instruction and an expandable instruction are read from an instruction cache. A tag compare and way selection unit checks to verify each instruction is a desired instruction. An instruction staging unit dispatches the expand instruction to a ... 08/04/05 - 20050172107 - Replay instruction morphing Replay instruction morphing. One disclosed apparatus includes an execution unit to execute an instruction. A replay system replays an altered instruction if the execution unit executes the instruction erroneously. ... 07/28/05 - 20050166038 - High-performance hybrid processor with configurable execution units A new general method for building hybrid processors achieves higher performance in applications by allowing more powerful, tightly-coupled instruction set extensions to be implemented in reconfigurable logic. New instructions set configurations can be discovered and designed by automatic and semi-automatic methods. Improved reconfigurable execution units support deep pipelining, addition of ... 07/14/05 - 20050154864 - Method and apparatus for nested control flow A method and apparatus for nested control flow includes a processor having at least one context bit. The processor includes a plurality of arithmetic logic units for performing single instruction multiple data (SIMD) operations. The method and apparatus further includes a first memory device storing a plurality of instructions wherein ... 07/07/05 - 20050149704 - Processor which accelerates execution of binary programs intended for execution on a conventional processor core, using a reconfigurable combinational logic array, a function lookup unit, and a compatible conventional processor core, without requiring rec The invention uses a standard processor to execute an application program. As the instructions of the application program are executed in sequence, a program counter is incremented to contain an address indicator of the next instruction to be executed. The address indicator from the program counter is also fed to ... 06/09/05 - 20050125642 - Dynamically reconfigurable logic circuit device, interrupt control method, and semi-conductor integrated circuit A dynamically reconfigurable logic circuit device includes a plurality of dynamically reconfigurable processor units (DRPU) arranged in array, and a plurality of dynamically connecting units (DCU). The dynamically connecting units interconnect inputs and outputs of the dynamically reconfigurable processor units. Each of the dynamically reconfigurable processor units includes a plurality ... ### FreshPatents.com Support |