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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Control > Processing Control For Data Transfer Processing Control For Data TransferProcessing Control For Data Transfer patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/28/06 - 20060218383 - Integrated circuit device An integrated circuit device having a CPU which performs given processing based on an instruction code, and a coprocessor which performs given calculation processing based on data supplied from the CPU and outputs a calculation result to the CPU. The CPU includes an immediate value generation section which generates immediate ... 09/28/06 - 20060218382 - Data processing disorder preventing method A data processing disorder preventing method applicable to a program having a plurality of processing procedures is proposed. The plurality of processing procedures serve to frequently process the same data block within a storage unit of a system, wherein the data block can only be processed by one processing procedure ... 09/21/06 - 20060212685 - Ultra low power asip architecture A microcomputer architecture comprises a microprocessor unit and a first memory unit, the microprocessor unit comprising a functional unit and at least one data register, the functional unit and the at least one data register being linked to a data bus internal to the microprocessor unit. The data register is ... 09/21/06 - 20060212684 - Circuit for monitoring a microprocessor and analysis tool and inputs/outputs thereof The invention relates to a method for the transmission of digital messages by means of the output terminals (22) of a monitoring circuit (18) which is integrated into a microprocessor (12), said digital messages being representative of first specific events which are dependent on the execution of a series of ... 08/10/06 - 20060179287 - Apparatus for controlling multi-word stack operations in digital data processors A digital data processor comprising a stack storage having a plurality of locations classified into two or more banks, and a stack pointer circuit pointing to one or more stack banks of the stack storage. The stack pointer circuit operates in response to decoding signals from an instruction decoder which ... 08/10/06 - 20060179286 - System and method for processing limited out-of-order execution of floating point loads A system for performing limited out-of order execution of floating point loads. The system includes a plurality of stages making up a pipeline, the stages including an early stage. The system also includes a mechanism for inputting an arithmetic instruction into the pipeline, the arithmetic instruction including a result address. ... 08/10/06 - 20060179285 - Type conversion unit in a multiprocessor system The invention relates to a very large instruction word (VLIW) processor, comprising a plurality of execution units (101, 103,105), a register file (109, 111, 113) and a communication network (117) for coupling the execution units and the register file. In case of an application specific VLIW processor, i.e. a VLIW ... 07/06/06 - 20060149939 - Multimedia coprocessor control mechanism including alignment or broadcast instructions A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes ... 07/06/06 - 20060149938 - Determining a register file region based at least in part on a value in an index register According to some embodiments, a value is retrieved from a location in an index register. A region in a register file may then be determined based at least in part on the value. Information may then be stored into the determined region of the register file. ... 07/06/06 - 20060149937 - Register file regions for a processing system According to some embodiments, a dynamic region in a register file may be described for an operand. The described region may, for example, store multiple data elements, each data element being associated with an execution channel of an execution engine. Information may then be stored into and/or retrieved from the ... 07/06/06 - 20060149936 - Processor core interface for external hardware modules and methods thereof A processor core architecture includes a cluster having at least a register file and predefined functional units having access to the register file. The architecture also includes an interface to one or more arbitrary functional units external to the processor core. The interface is to provide the arbitrary functional units ... 05/04/06 - 20060095741 - Store instruction ordering for multi-core processor A method and apparatus for minimizing stalls in a pipelined processor is provided. Instructions in an out-of-order instruction scheduler are executed in order without stalling the pipeline by sending store data to external memory through an ordering queue. ... 02/02/06 - 20060026399 - Information processing unit and store instruction control method In order to increase the operation efficiency of the operation register for holding store data when executing store instruction to store data in a predetermined store area on the main memory or the cache memory, in the present invention, an instruction processing section is adapted so as, when an operation ... 12/22/05 - 20050283591 - System and method for handling load and/or store operations in a superscalar microprocessor The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of ... 12/15/05 - 20050278511 - Reconstructing transaction order using clump tags A method and system for enforcing ordering rules for transactions are presented. The method and system generates transaction clump tags for each transaction before the transactions are stored in various type specific transaction queues. A transaction clump tag decoding unit decodes the transaction clump tag to recover temporal information regarding ... 11/10/05 - 20050251660 - Method and system for specualtively sending processor-issued store operations to a store queue with full signal asserted A method and processor chip design for enabling a processor core to continue sending store operations speculatively to the store queue after the core receives indication that the store queue is full. The processor core is configured with speculative store logic that enables the processor core to continue issuing store ... 11/10/05 - 20050251659 - Methods and apparatus for indexed register access Methods and apparatus enable the execution of processing sequences including the computation of a register index that is loaded into one of a plurality of registers, utilizing that index to identify another of the plurality of registers, and accessing data from or copying data to the indexed register to or ... 10/13/05 - 20050228975 - Architected register file extension in a multi-thread processor An apparatus, a method, and a computer program are provided for an architected register file system for multithread system. In conventional architected register file systems, a thread is only capable of utilizing a single register file. However, when register files of other thread are unused, the system resources are wasted. ... 09/15/05 - 20050204118 - Method for inter-cluster communication that employs register permutation The present invention is a method for inter-cluster communication that employs register permutation by dynamically mapping the registers to the functional units. Because only the mapping between registers and functional units is changed and no actual data movement occurs, the present invention greatly diminishes the power consumption. Owing to the ... 08/25/05 - 20050188184 - System and method for handling load and/or store operations an a supperscalar microprocessor The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of ... 08/25/05 - 20050188183 - Digital signal processor having data address generator with speculative register file Methods and apparatus for handling speculative addresses in a pipelined digital processor are provided. A digital signal processor includes an address generator configured to generate speculative data addresses, a pipelined execution unit configured to execute instructions using data at locations specified by the speculative data addresses, a speculative register file ... 07/14/05 - 20050154863 - Multi-processor system utilizing speculative source requests Multi-processor systems and methods are disclosed that employ speculative source requests to obtain speculative data fills in response to a cache miss. In one embodiment, a source processor generates a speculative source request and a system source request in response to a cache miss. At least one processor provides a ... 07/07/05 - 20050149703 - Utilizing an advanced load address table for memory disambiguation in an out of order processor Embodiments include a system for minimizing storage space required for tracking load instructions through a pipeline in a processor. Store instructions are tracked in a separate queue and only load instructions that require speculation on data or addresses are tracked in a load table and flagged in the reorder buffer. ... 07/07/05 - 20050149702 - Method and system for memory renaming Embodiments of the present invention provide a method, apparatus and system for memory renaming. In one embodiment, a decode unit may decode a load instruction. If the load instruction is predicted to be memory renamed, the load instruction may have a predicted store identifier associated with the load instruction. The ... 06/30/05 - 20050144424 - Vliw processor with data spilling means A VLIW processor comprising: a plurality of functional units (1, 3); a distributed register file (4) comprising a plurality of segments (5, 7, 9), the distributed register file (4) being accessible by the functional units (1, 3); a communication unit (11) for communication with a memory; a communication network (13) ... 06/23/05 - 20050138339 - Method for and a trailing store buffer for use in memory renaming Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient memory renaming. The method includes computing a store address, writing the store address in a first storage, writing data associated with the store address to a memory, and de-allocating the store address from the ... 06/23/05 - 20050138338 - Register alias table cache Embodiments of the present invention relate to a system and method for implementing functions of a register translation table of a computer processor, with reduced area requirements as compared to known arrangements. ... 06/09/05 - 20050125641 - Data processing apparatus and method for moving data between registers and memory A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements ... 06/09/05 - 20050125640 - Data processing apparatus and method for moving data between registers and memory A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements ... 06/09/05 - 20050125639 - Table lookup operation within a data processing system A table lookup extension instruction is provided in which index values stored within an index register D2 are used to select data elements stored within one or more table registers D0, D1 for storage into corresponding positions within a result register D3. Out-of-range index values result in the corresponding locations ... ### FreshPatents.com Support |