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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Control > Arithmetic Operation Instruction Processing Arithmetic Operation Instruction ProcessingArithmetic Operation Instruction Processing patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/05/06 - 20060224865 - Vector processing system A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation ... 09/14/06 - 20060206695 - Data movement within a processor A processor, e.g., a VLIW processor, may include two separate execution units, a first execution unit may have a general-purpose register file and an arithmetic logic unit. The register file may source operands to the ALU, and the result of the ALU operation may be stored in the register file ... 09/14/06 - 20060206694 - Parsing-enhancement facility An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general register, wherein a first general register stores an ... 08/31/06 - 20060195680 - Computer instruction value field having an embedded sign A computer machine instruction is fetched and executed, the machine instruction having a signed field value wherein the signed field value comprises contiguous bit positions 1-N consisting of a contiguous most significant value contiguous with a contiguous embedded sign field, the embedded sign field contiguous with a contiguous least significant ... 08/24/06 - 20060190708 - Multifunction hexadecimal instruction form A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point ... 08/17/06 - 20060184773 - Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted ... 05/18/06 - 20060107027 - General purpose micro-coded accelerator A micro-coded accelerator may comprise multiple programmable control units, multiple special function units, a cross-bar switch to connect any of the control units to any one or more of the special function units, and a global memory to facilitate processing by these units. Each control unit may have an array ... 05/11/06 - 20060101245 - Apparatus and method for matrix data processing A matrix data processor is implemented wherein data elements are stored in physical registers and mapped to logical registers. After being stored in the logical registers, the data elements are then treated as matrix elements. By using a series of variable matrix parameters to define the size and location of ... 05/11/06 - 20060101244 - Multipurpose functional unit with combined integer and floating-point multiply-add pipeline A multipurpose functional unit is configurable to support a number of operations including floating-point and integer multiply-add, operations as well as other integer and/or floating-point arithmetic operations, Boolean operations, comparison testing operations, and format conversion operations. ... 05/11/06 - 20060101243 - Multipurpose functional unit with multiply-add and logical test pipeline A multipurpose functional unit is configurable to support a number of operations including multiply-add and comparison testing operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and format conversion operations. ... 05/11/06 - 20060101242 - Multipurpose multiply-add functional unit A multipurpose functional unit is configurable to support a number of operations including multiply-add and comparison testing operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and format conversion operations. ... 05/04/06 - 20060095740 - Apparatus and methods for utilization of splittable execution units of a processor A partial execution unit of a splittable execution unit performs an operation on a portion of one or more arguments of a micro-operation to generate a first partial execution result of the micro-operation. A complementary portion of one of the arguments is passed through a bypass execution unit instead of ... 05/04/06 - 20060095739 - Simd processor executing min/max instructions A SIMD processor responds to a single min/max instruction to find the minimum or maximum valued data unit in an array of data units. The determined minimum/maximum value and an associated index value thereto may be output. Alternatively, the value of a data unit in another array may be output ... 04/06/06 - 20060075211 - Method and device for data processing Designing a coupling of a traditional processor, in particular a sequential processor, and a reconfigurable field of data processing units, in particular a runtime-reconfigurable field of data processing units is described. ... 02/02/06 - 20060026394 - Optimizing data manipulation in media processing applications A system comprising a processor containing a first stack internal to a core of the processor, at least some data values in the first stack corresponding to values in a second stack external to the core. The system also comprises a memory coupled to the processor. In an iterative process, ... 02/02/06 - 20060026393 - Splitting execution of instructions between hardware and software In some embodiments, a processor comprises fetch logic that fetches instructions, an integer pipeline, and a hardware state machine that is separate from and interacts with the integer pipeline. The instruction is executed partly in the integer pipeline according to software and partly in the hardware state machine. ... 11/10/05 - 20050251658 - Processing unit A digital signal processing unit includes a control unit and a data computing unit. An R/L register for distinguishing independent data is disposed in the control unit. An R/L select signal for indicating independent data is supplied to the data computing unit. A data processing instruction signal for distinguishing a ... 09/08/05 - 20050198473 - Multiplexing operations in simd processing A data processing apparatus, method and computer program product. The apparatus comprising: a register data store comprising at least three general purpose registers each operable to store a plurality of data elements; an instruction decoder operable to decode a multiplex instruction; a data processor operable to process said plurality of ... 08/11/05 - 20050177705 - Pop-compare micro instruction for repeat string operations A microprocessor apparatus is provided for performing a pop-compare operation. The microprocessor apparatus includes paired operation translation logic, load logic, and execution logic. The paired operation translation logic receives a macro instruction that prescribes the pop-compare operation, and generates a pop-compare micro instruction. The pop-compare micro instruction directs pipeline stages ... 07/07/05 - 20050149701 - Method, apparatus and system for pair-wise minimum and minimum mask instructions A method, apparatus, and system for pair-wise minimum and minimum mask instructions are generally presented. ... 06/23/05 - 20050138337 - Processor and method for a simultaneous execution of a calculation and a copying process A processor includes a source register having a source register content, a destination register, a calculating unit for performing a calculation using the source register content, wherein the calculation is performed in several calculation cycles, and wherein in each cycle only one portion of the source register content is useable, ... 06/09/05 - 20050125638 - Data shift operations A data processing apparatus and method. The data processing apparatus comprising: a register data store operable to store data elements; an instruction decoder operable to decode a shift instruction; a data processor operable to perform data processing operations controlled by said instruction decoder wherein: in response to said decoded shift ... 06/09/05 - 20050125637 - Constant generation in simd processing A data processing apparatus (2) comprising: a register data store operable to store data elements; an instruction decoder (14, 16) operable to decode an instruction with generated constant, said instruction having a data value associated therewith; a data processor. (18) operable to perform data processing operations within parallel processing lanes ... 06/09/05 - 20050125636 - Vector by scalar operations A data processing apparatus is disclosed. The apparatus comprises a register data store comprising a plurality of registers. The apparatus further comprises a data processor operable to perform in parallel a data processing operation on data elements; and decode logic responsive to a single vector-by-scalar instruction to control the data ... 06/09/05 - 20050125635 - Moving data between registers of different register data stores A data processing system 2 is provided including a scalar register store 4 and a SIMD register store 20. Dedicated register transfer instructions are provided which serve to move a data value between a selected data element position/lane within a SIMD register of the SIMD register data store 20 and ... ### FreshPatents.com Support |