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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Control Processing ControlProcessing Control patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/21/06 - 20060212683 - Information processing system, pipeline processor, and computer readable recording medium in which busy judgment program is stored In the present invention, in order that a busy judgment of a register can be made without fail and without increasing the number of hardware resources for storing a request into the register provided at the final stage of a pipeline register in a stage in which the request is ... 09/07/06 - 20060200652 - Method for signaling of a state or of an event A first component is signaled from a second component by a status signal that a state or an event which requires a reaction has occurred. First data items are stored in the second component which can be set to a specific value by the second component and can be reset ... 09/07/06 - 20060200651 - Method and apparatus for power reduction utilizing heterogeneously-multi-pipelined processor A processor includes a common instruction decode front end, e.g. fetch and decode stages, and a heterogeneous set of processing pipelines. A lower performance pipeline has fewer stages and may utilize lower speed/power circuitry. A higher performance pipeline has more stages and utilizes faster circuitry. The pipelines share other processor ... 09/07/06 - 20060200650 - Single-cycle low-power cpu architecture An n architecture for implementing an instruction pipeline within a CPU comprises an arithmetic logic unit (ALU), an address arithmetic unit (AAU), a program counter (PC), a read-only memory (ROM) coupled to the program counter, to an instruction register, and to an instruction decoder coupled to the arithmetic logic unit. ... 09/07/06 - 20060200649 - Data alignment and sign extension in a processor A method comprising loading a plurality of data bytes from a data cache in response to a load instruction, determining the most significant bit of at least one of the data bytes using a first logic, arranging at least some of the data bytes onto a data bus using a ... 12/01/05 - 20050268074 - Method and apparatus for determining the criticality of a micro-operation A method and apparatus for whacking a μOP based upon the criticality of that μOP. Also disclosed are embodiments of a method for determining the criticality of a μOP. ... 09/22/05 - 20050210223 - Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor One embodiment of the present invention provides a system that dynamically adjusts the aggressiveness of an execute-ahead processor. If a data-dependent stall condition is encountered during program execution, the system enters an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred, and other ... 09/22/05 - 20050210222 - Optimized ordering of firmware modules A method and system to optimize ordering of firmware modules. Optimizing the dispatch order of firmware modules reduces the boot time of a computer system. A plurality of module-to-module interfaces are collected from a plurality of firmware modules, wherein a module-to-module interface allows a first firmware module of the plurality ... 08/25/05 - 20050188181 - Data bus configuration A system includes logic configured for counting transitions between data on a bus and data to be put onto the bus. Where the counted transitions exceed a threshold, the data to be put onto the bus is complemented. As a result, complemented data is put on the bus where the ... 07/28/05 - 20050166037 - Method of avoiding flush due to store queue full in a high frequency system with a stall mechanism and no reject mechanism An apparatus, a method, and a computer program are provided for stalling the performance of commands. In a normal performance system, there are multiple steps that have to be complete for a command to be performed. However, commands may not be performed for a variety of reasons. Typically, a system ... 07/07/05 - 20050149700 - Virtual multithreading translation mechanism including retrofit capability Method, apparatus and system embodiments provide support for multiple SoEMT software threads on multiple SMT logical thread contexts. A thread translation table maintains physical-to-virtual thread translation information in order to provide such information to structures within a processor that utilize virtual thread information. By associating a thread translation table with ... 06/23/05 - 20050138336 - Component processing system and component processing method To provide a component processing system and a component processing method in which components used by a plurality of applications are centrally managed, thereby enabling efficient response to changes in the components. Component environment definition information that shows locations of components used by the individual applications is composed of a ... 06/02/05 - 20050120192 - Scalable rename map table recovery Checkpoints may be used to recover from branch mispredictions using scalable rename map table recovery. ... ### FreshPatents.com Support |