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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Dynamic Instruction Dependency Checking, Monitoring Or Conflict Resolution > Reducing An Impact Of A Stall Or Pipeline Bubble Reducing An Impact Of A Stall Or Pipeline BubbleReducing An Impact Of A Stall Or Pipeline Bubble patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/05/06 - 20060224864 - System and method for handling multi-cycle non-pipelined instruction sequencing A system and method for handling multi-cycle non-pipelined instruction sequencing. With the system and method, when a non-pipelined instruction is detected at an issue point, the issue logic initiates a stall that is for a minimum number of cycles that the fastest non-pipelined instruction could complete. The execution unit then ... 08/24/06 - 20060190707 - System and method of correcting a branch misprediction When a branch misprediction in a pipelined processor is discovered, if the mispredicted branch instruction is not the last uncommitted instruction in the pipelines, older uncommitted instructions are checked for dependency on a long latency operation. If one is discovered, all uncommitted instructions are flushed from the pipelines without waiting ... 08/10/06 - 20060179284 - Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline detects a stalling event caused by a dispatched instruction, and flushes the execution pipeline to enable instructions ... 07/13/06 - 20060155967 - Processing essential and non-essential code separately A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the ... 07/06/06 - 20060149935 - Load lookahead prefetch for microprocessors The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The data for such ... 07/06/06 - 20060149934 - Using a modified value gpr to enhance lookahead prefetch The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The execution of such future ... 07/06/06 - 20060149933 - Branch lookahead prefetch for microprocessors A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during execution of the program instructions, speculatively executing one or more pending instructions which include at least one branch instruction during the stall condition, and ... 05/04/06 - 20060095738 - Back-end renaming in a continual flow processor pipeline Embodiments of the present invention relate to a system and method for comparatively increasing processor throughput and relieving pressure on the processor's scheduler and register file by diverting instructions dependent on long-latency operations from a flow of the processor pipeline and re-introducing the instructions into the flow when the long-latency ... 05/04/06 - 20060095737 - Methods and apparatus for pipelined processing In a first aspect, a first method is provided for pipelined processing. The first method includes the steps of (1) receiving a first instruction in an in-order execution processing pipeline; and (2) receiving a second instruction in the in-order execution processing pipeline before execution of the first instruction completes. The ... 07/07/05 - 20050149699 - Variable length instruction pipeline A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline stalls. The expansion stages are removed from the variable length instruction pipeline when not needed to reduce the length of the pipeline, which reduces latency and other problems ... ### FreshPatents.com Support |