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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Dynamic Instruction Dependency Checking, Monitoring Or Conflict Resolution > Commitment Control Or Register Bypass Commitment Control Or Register BypassCommitment Control Or Register Bypass patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/28/06 - 20060218380 - Add-shift-round instruction with dual-use source operand for dsp dest:=(A+B+C+D . . . +M+2N−1)>>N ... 09/14/06 - 20060206693 - Method and apparatus to execute an instruction with a semi-fast operation in a staggered alu A method for executing an instruction with a semi-fast operation in a staggered ALU. The method of one embodiment comprises generating a first operation and a second operation from a micro-instruction. The first and second operations are scheduled for execution in a staggered arithmetic logic unit (ALU). The first and ... 08/24/06 - 20060190706 - Processor utilizing novel architectural ordering scheme Various methods, apparatuses, and systems in which a processor includes an issue engine and an in-order execution pipeline. The issue engine categorizes operations as at least one of either a speculative operation which perform computations or an architectural operation which has potential to fault or cause an exception. Each architectural ... 08/24/06 - 20060190705 - Processor utilizing novel architectural ordering scheme Various methods, apparatuses, and systems in which a processor includes an issue engine and an in-order execution pipeline. The issue engine categorizes operations as at least one of either a speculative operation which perform computations or an architectural operation which has potential to fault or cause an exception. Each architectural ... 08/17/06 - 20060184772 - Lookahead mode sequencer A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data structure for storing data within the processor. The mechanism of the present invention comprises a data structure including information used by the ... 08/17/06 - 20060184771 - Mini-refresh processor recovery as bug workaround method using existing recovery hardware A method in a data processing system for avoiding a microprocessor's design defects and recovering a microprocessor from failing due to design defects, the method comprised of the following steps: The method detects and reports of events which warn of an error. Then the method locks a current checkpointed state ... 08/10/06 - 20060179283 - Return data selector employing barrel-incrementer-based round-robin apparatus A return data selector is disclosed. A pipelined microprocessor includes N functional units that request to return data to the pipeline. In a given selection cycle, some of the functional units may not be requesting to return data. The return data selector includes a circuit for selecting one of functional ... 07/27/06 - 20060168425 - Method and system of aligning execution point of duplicate copies of a user program by exchanging information about instructions executed A method and system of aligning execution point of duplicate copies of a user program by exchanging information about instructions executed. At least some of the exemplary embodiments may be a method comprising operating duplicate copies of a user program in a first and second processor, allowing at least one ... 07/13/06 - 20060155966 - Processor including a register file and method for computing flush masks in a multi-threaded processing system A processor including a register file and method for computing flush masks in a multi-threaded processing system provides fast and low-logic-overhead computation of a flush result in response to multiple flush request sources. A flush mask register file is implemented by multiple cells in an array where cells are absent ... 07/06/06 - 20060149932 - Data processing circuit, multiplier unit with pipeline, alu and shift register unit for use in a data processing circuit The present invention provides a circuit of processing integer data, especially for graphic applications having a multiplier unit which includes a pipeline in which the word length is adjustable for multiplying integer data s words of 8 bits or multiples thereof an arithmetic logic unit (ALU) for performing arithmetic operations ... 07/06/06 - 20060149931 - Runahead execution in a central processing unit According to one embodiment, a method is disclosed. The method includes detecting a load miss at a central processing unit (CPU), stalling a read only buffer (ROB), speculatively retiring an instruction causing the ROB stall and subsequent instructions, keeping registers that have not been renamed in the ROB upon retirement, ... 07/06/06 - 20060149930 - Systems and methods for improving performance of a forwarding mechanism in a pipelined processor Systems and methods for forwarding instruction results from various pipeline stages to the initial stages of the pipelines, where the results can be used in the execution of subsequent instructions. In one embodiment, a forwarding mechanism is designed so that sets of one or more dynamic data selection circuits are ... 05/25/06 - 20060112261 - Method and apparatus for incremental commitment to architectural state in a microprocessor Method and hardware apparatus are disclosed for reducing the rollback penalty on exceptions in a microprocessor executing traces of scheduled instructions. Speculative state is committed to the architectural state of the microprocessor at a series of commit points within a trace, rather than committing the state as a single atomic ... 05/04/06 - 20060095736 - Clustered superscalar processor and communication control method between clusters in clustered superscalar processor A clustered superscalar processor for reducing the miss rate of a register cache and reducing the possibility of miss penalties. The processor checks before storing an instruction in an instruction window whether there is a data dependency relationship between the instruction that will be stored in the instruction window and ... 05/04/06 - 20060095735 - Systems and methods for increasing register addressing space in instruction-width limited processors A system for executing instructions is presented. In some embodiments, among others, the system comprises functional units, local multiplexers, local register files, and a global register file, which are communicatively coupled to each other and arranged to accommodate shortened instruction words in multiple-issue processors. These components are arranged to permit ... 05/04/06 - 20060095734 - Processor with dependence mechanism to predict whether a load is dependent on older store A processor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store unit. In response to detection of incorrect data speculation ... 12/29/05 - 20050289326 - Packet processor with mild programmability A reduced instruction set pipelined processor having an instruction fetch stage, an instruction decode stage, an executive stage and a write back stage and programmed with a single program which is structured to implement a function performed by a finite state machine. Only read after write data hazards exist in ... 12/22/05 - 20050283590 - Reducing false error detection in a microprocessor by tracking dynamically dead instructions A technique to reduce false error detection in microprocessors by tracking dynamically dead instructions. When an instruction commits, it is then stored in a PET buffer. A processor may now declare a machine check error when the instruction is being removed from the PET buffer rather than at the commit ... 12/15/05 - 20050278510 - Pseudo register file write ports A system comprising execution circuitry for executing instructions and a register file comprising at least one port, the circuitry operating to allow said execution circuitry to share a common port of said register file. ... 12/08/05 - 20050273580 - Avoiding register raw hazards when returning from speculative execution One embodiment of the present invention provides a system that avoids register read-after-write (RAW) hazards upon returning from a speculative-execution mode. This system operates within a processor with an in-order architecture, wherein the processor includes a short-latency scoreboard that delays issuance of instructions that depend upon uncompleted short-latency instructions. During ... 12/08/05 - 20050273579 - Method and apparatus for maintaining status coherency between queue-separated functional units An apparatus and method in a microprocessor having two unaligned functional unit pipelines which enables an instruction queue for the second pipeline to be placed at an intermediate pipeline stage rather than after the stage in the first pipeline that retires instructions. The apparatus maintains coherency between the status of ... 11/10/05 - 20050251657 - Methods and systems for grouping and managing memory instructions Methods, systems, and articles of manufacture consistent with the present invention provide a memory instruction manager for managing the execution of instructions associated with a program. The memory instruction manager assigns a first group identifier to a first instruction associated with a program and to a second instruction associated with ... 11/10/05 - 20050251656 - Computer system The computer system presented comprises a data file having entries each designed to hold data, an advanced and a completed mapping file each having entries each designed to hold a data-file-entry address, a state-modification queue having entries each designed to hold substance of a modification made on the advanced mapping ... 10/13/05 - 20050228973 - System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block ... 10/13/05 - 20050228972 - Completion table configured to track a larger number of outstanding instructions A method, completion table and processor for tracking a larger number of outstanding instructions. The completion table may include a plurality of entries where each entry tracks a consecutive number of outstanding instructions. Each entry may be configured to store an instruction address and an identification of a first of ... 09/29/05 - 20050216707 - Configurable microprocessor architecture incorporating direct execution unit connectivity An architecture for a highly configurable and scalable microprocessor architecture designed for exploiting instruction level parallelism in specific application code. It consists of a number of execution units with configurable connectivity between them and a means to copy data through execution units under software control. ... 09/08/05 - 20050198472 - Digital signal processors with configurable dual-mac and dual-alu DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU configuration, a single-MAC/dual-ALU configuration, or ... 08/18/05 - 20050182918 - Pipelined microprocessor, apparatus, and method for generating early instruction results An apparatus and method for providing early instruction results is disclosed. Early execution logic, comprising an enhanced address generator located in an address generation stage of the microprocessor pipeline, receives input operands and generates early results of instructions reaching the address stage prior to final execution units (in lower pipeline ... 06/23/05 - 20050138335 - Methods and apparatus to control power consumption within a processor Methods and apparatus are disclosed to control power consumption within a processor. An example processor disclosed herein comprises an instruction retirement unit; a first set of functional blocks to process a first set of instructions having a first instruction type; a second set of functional blocks to process a second ... 06/23/05 - 20050138334 - Late allocation of registers Embodiments of the present invention relate to a method and system for providing virtual identifiers corresponding to physical registers in a computer processor. According to the embodiments, the virtual identifiers may be used to represent the physical registers during operations in a pipeline of the processor. ... 06/23/05 - 20050138333 - Thread switching mechanism Method, apparatus and system embodiments provide support for multiple SoEMT software threads on multiple SMT logical processors. A thread switch on a given logical processor may be accomplished without interrupting operation of other physical threads. Microarchitectural state for a current virtual thread is “torpedoed” at a torpedo point before a ... 06/23/05 - 20050138332 - Method and apparatus for results speculation under run-ahead execution A method and apparatus for using result-speculative data under run-ahead speculative execution is disclosed. In one embodiment, the uncommitted target data from instructions being run-ahead executed may be saved into an advance data table. This advance data table may be indexed by the lines in the instruction buffer containing the ... 06/09/05 - 20050125634 - Processor and instruction control method The processor issues instructions including a branch instruction under a first identifier (ID=0) and speculatively executes the instructions by branch prediction. In the event of the detection of a branch error, the processor issues instructions in the correct direction under a second identifier (ID=1) subsequently to the erroneously issued instructions. ... ### FreshPatents.com Support - Terms & Conditions |