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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Dynamic Instruction Dependency Checking, Monitoring Or Conflict Resolution > Scoreboarding, Reservation Station, Or Aliasing Scoreboarding, Reservation Station, Or AliasingScoreboarding, Reservation Station, Or Aliasing patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.08/24/06 - 20060190704 - Apparatus for increasing addressability of registers within a processor An apparatus for increasing addressability of registers within a processor is disclosed. The apparatus includes a set of apparent registers and a set of real registers. The total number of real registers is substantially higher than the total number of apparent registers such that only a subset of the real ... 08/10/06 - 20060179282 - Method using hazard vector to enhance issue throughput of dependent instructions in a microprocessor A method and related apparatus is provided for a processor having a number of registers, wherein instructions are sequentially issued to move through a sequence of execution stages, from an initial stage to a final write back stage. As a method, an embodiment includes the step of issuing a first ... 08/03/06 - 20060174093 - System and method for event based interportlet communications In accordance with embodiments, there are provided mechanisms and methods for configuring and executing portlet responses to events within a web portal framework. These mechanisms and methods can enable event descriptions to be organized within a portlet configuration file with event handlers designated for responding to the event. As used ... 07/06/06 - 20060149929 - Processor with automatic scheduling of operations A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when an operand ... 06/08/06 - 20060123219 - Intra-instruction fusion Fusing micro-operations (uops) together. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in a cache memory, un-fused, executed in parallel, and retired in order to optimize cost and performance. ... 05/04/06 - 20060095733 - Hardware device for executing conditional instruction out-of-order fetch and execution method thereof A hardware device for executing conditional instructions out-of-order and the execution method. An architecture is provided, enabling the hardware device such as a processor supporting the conditional instruction and a computer system to execute the instruction out-of-order. To this end, a conditional execution buffer is provided, and a register of ... 05/04/06 - 20060095732 - Processes, circuits, devices, and systems for scoreboard and other processor improvements A method of instruction issue (3200) in a microprocessor (1100, 1400, or 1500) with execution pipestages (E1, E2, etc.) and that executes a producer instruction Ip and issues a candidate instruction I0 (3245) having a source operand dependency on a destination operand of instruction Ip. The method includes issuing the ... 05/04/06 - 20060095731 - Method and apparatus for avoiding read port assignment of a reorder buffer An out-of-order subsystem of a processor includes a register alias table and allocation (RAT/ALLOC) unit, a reservation station (RS) and a reorder buffer (ROB). Destination identifiers of one or more execution results that are not yet stored in any register file of the ROB may be compared to source identifiers ... 01/26/06 - 20060020773 - System and method for register renaming A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A ... 12/22/05 - 20050283589 - Data processor An input pointer update circuit updates an input pointer in response to the value of an RBC latch, the input pointer of a BIP latch and input pointer update information from an instruction decoding unit (first decoder) when the value of an RM latch is “1”. An output pointer update ... 12/22/05 - 20050283588 - Instruction control apparatus, function unit, program conversion apparatus, and language processing apparatus The invention relates to an instruction control apparatus, a function unit, a program conversion apparatus, and a language processing apparatus. An object of the invention is to alter and add functions to the above apparatuses inexpensively and freely. To this end, in an instruction control apparatus according to the invention ... 10/13/05 - 20050228971 - Buffer virtualization A buffer virtualization mechanism to allow for a large number of allocate-able buffering resources. In particular, embodiments of the invention involve a tracking technique for implementing the use of virtual buffers within a microprocessor architecture. ... 09/29/05 - 20050216706 - Executing partial-width packed data instructions A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming ... 07/07/05 - 20050149698 - Scoreboarding mechanism in a pipeline that includes replays and redirects An apparatus for a processor includes a first scoreboard, a second scoreboard, and a control circuit coupled to the first scoreboard and the second scoreboard. The control circuit is configured to update the first scoreboard to indicate that a write is pending for a first destination register of a first ... 06/16/05 - 20050132172 - Method and apparatus for eliminating the need for register assignment, allocation, spilling and re-filling A method and apparatus is provided to manage data in computer registers in a program, making more computer registers available to one or more programmers utilizing a name level instruction. The method and apparatus disclosed herein presents a way of reducing the overhead of register management, by introducing a concept ... 06/16/05 - 20050132171 - Method for register allocation during instruction scheduling The present disclosure relates to the allocation of registers the scheduling of instructions, and, more specifically, to the classifying of operands and allocation of registers to local operands. ... 06/02/05 - 20050120191 - Checkpoint-based register reclamation A processor enabled with checkpoints may be used to recover registers using counter entry and release. ... ### FreshPatents.com Support |