REGISTER now for FREE 
|
FREE patent keyword monitoring and additional FREE benefits. REGISTER now for FREE
|
|
|
Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Dynamic Instruction Dependency Checking, Monitoring Or Conflict Resolution Dynamic Instruction Dependency Checking, Monitoring Or Conflict ResolutionDynamic Instruction Dependency Checking, Monitoring Or Conflict Resolution patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.08/17/06 - 20060184770 - Method of implementing precise, localized hardware-error workarounds under centralized control In a processor, a localized workaround is activated upon the sensing of a problematic condition occurring on said processor, and then control of the deactivation of the localized workaround is superseded by a centralized controller. In a preferred embodiment, the centralized controller monitors forward progress of the processor and maintains ... 08/17/06 - 20060184769 - Localized generation of global flush requests while guaranteeing forward progress of a processor Localized generation of global flush requests while providing a means for increasing the likelihood of forward progress in a controlled fashion. Local hazard (error) detection is accomplished with a trigger network situated between execution units and configurable state machines that track trigger events. Once a hazardous state is detected, a ... 12/08/05 - 20050273578 - Systems and methods for efficient manual windowing operation A method and system of manual windowing within a displayed image is disclosed, which include specifying different windows within a displayed image, assigning tags to different windows, assigning processing channels to the windows, processing the different windows on the basis of the assigned tags and assembling the different windows. A ... 09/29/05 - 20050216705 - Data dependency detection using history table of entry number hashed from memory address A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, ... 08/25/05 - 20050188180 - Dynamic control of computer resources for the pipeline processing of data using anytime algorithms Dynamic control of computer resources is used for processing process data in a pipeline. The pipeline includes a multiplicity of pipeline processors which each operate on the basis of an anytime approach and which can generate a result at a settable time. By detecting the runtime behavior of the pipeline ... 07/14/05 - 20050154862 - Mechanism for processing speculative ll and sc instructions in a pipelined processor A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one reservation is valid in the processor. A reservation is established responsive to processing a load-linked instruction, which is a load instruction that is ... 07/14/05 - 20050154861 - Method and data processing system having dynamic profile-directed feedback at runtime According to a method of operating a data processing system, software communicates to a processing unit a classification each of at least one schedulable software entity that the processing unit executes. A resource manager within the processing unit dynamically allocates hardware resources within the processing unit to the schedulable software ... 07/14/05 - 20050154860 - Method and data processing system optimizing performance through reporting of thread-level hardware resource utilization According to a method of operating a data processing system, one or more monitoring parameter sets are established in a processing unit within the data processing system. The processing unit monitors, in hardware, execution of each of a plurality of schedulable software entities within the processing unit in accordance with ... ### FreshPatents.com Support |