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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Instruction Issuing > Simultaneous Issuance Of Multiple Instructions Simultaneous Issuance Of Multiple InstructionsSimultaneous Issuance Of Multiple Instructions patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/05/06 - 20060224863 - Preparing instruction groups for a processor having multiple issue ports Disclosed is a mechanism of preparing an instruction group 606 using a plurality of pools 700 having a hierarchical structure 711-715. Each pool represents a different overlapping subset of the issue ports 610. Placing an instruction 600 into a particular pool 700 also reduces vacancies in any one or more ... 09/14/06 - 20060206692 - Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessor A dispatch scheduler in a multithreading microprocessor is disclosed. Each of N concurrently executing threads has one of P priorities. P N-bit round-robin vectors are generated, each being a 1-bit left-rotated and subsequently sign-extended version of an N-bit 1-hot input vector indicating the last thread selected for dispatching at the ... 08/17/06 - 20060184768 - Method and apparatus for dynamic modification of microprocessor instruction group at dispatch Dynamic reformatting of a dispatch group by selective activation of inactive Start bits of instructions within the dispatch group at the time the instructions are read from the IBUF. The number of instructions in the reformatted dispatch groups can vary from as few as one instruction per group to a ... 08/03/06 - 20060174092 - Fetch-side instruction dispatch group formation An improved method, apparatus, and computer instructions for grouping instructions. A set of instructions is received for placement into an instruction cache in the data processing system. Instructions in the set of instructions are grouped into a dispatch grouping of instructions prior to the set of instructions being placed in ... 07/13/06 - 20060155965 - Method and apparatus for control signals memoization in a multiple instruction issue microprocessor A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register ... 05/11/06 - 20060101241 - Instruction group formation and mechanism for smt dispatch A more efficient method of handling instructions in a computer processor, by associating resource fields with respective program instructions wherein the resource fields indicate which of the processor hardware resources are required to carry out the program instructions, calculating resource requirements for merging two or more program instructions based on ... 05/04/06 - 20060095730 - Expansion of compute engine code space by sharing adjacent control stores using interleaved program addresses Method and apparatus to support expansion of compute engine code space by sharing adjacent control stores using interleaved addressing schemes. Instructions corresponding to an original instruction thread are partitioned into multiple interleaved sequences that are stored in respective control stores. During thread execution, instructions are retrieved from the control stores ... 10/06/05 - 20050223196 - Apparatus and method for asymmetric dual path processing According to embodiments of the invention, there is disclosed a computer processor architecture; and in particular a computer processor, a method of operating the same, and a computer program product that makes use of an instruction set for the computer. In one embodiment according to the invention, there is provided ... 06/16/05 - 20050132170 - Multi-issue processor A multi-issue processor comprises a plurality of issue slots (UC0, UC1, UC2 and UC3), each one of the plurality of issue slots having a plurality of functional units (FU0, FU1 and FU2) and a plurality of holdable registers (1-33 and 101-117). The plurality of issue slots comprises a first set ... ### FreshPatents.com Support |