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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Instruction Issuing Instruction IssuingInstruction Issuing patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/05/06 - 20060224862 - Mixed superscalar and vliw instruction issuing and processing method and system Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal processor receives in a mixed instruction listing a plurality of digital signal processor instructions. The plurality of digital signal processor instructions includes a plurality ... 09/21/06 - 20060212682 - Processor utilizing novel architectural ordering scheme Various methods, apparatuses, and systems in which a processor includes an issue engine and an in-order execution pipeline. The issue engine categorizes operations as at least one of either a speculative operation which perform computations or an architectural operation which has potential to fault or cause an exception. Each architectural ... 09/21/06 - 20060212681 - Processor and method of grouping and executing dependent instructions in a packet An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a first execution unit for execution and generating a first result, steering a second instruction of the instruction packet to a second execution unit for ... 09/07/06 - 20060200648 - High-level language processor apparatus and method A digital computing component and method for computing configured to execute the constructs of a high-level software programming language via optimizing hardware targeted at the particular high-level software programming language. The architecture employed allows for parallel execution of processing components utilizing instructions that execute in an unknown number of cycles ... 08/31/06 - 20060195679 - Processing apparatus A processing apparatus includes an execution stage which executes each of instruction streams, a first resource counter which counts the number of operating resources used when the execution stage executes a first one of the instruction streams, a second resource counter which holds data of the number of unused ones ... 08/24/06 - 20060190703 - Programmable delayed dispatch in a multi-threaded pipeline Detecting a stall condition associated with processor instructions within one or more threads and generating a no-dispatch condition. The stall condition can be detected by hardware and/or software before and/or during processor instruction execution. The no-dispatch condition can be associated with a number of processing cycles and an instruction from ... 08/17/06 - 20060184767 - Dynamic recalculation of resource vector at issue queue for steering of dependent instructions A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instructions, from threads being processed simultaneously, to shared ... 08/10/06 - 20060179281 - Multithreading instruction scheduler employing thread group priorities A multithreading processor with an efficient and fair thread scheduler is disclosed. The scheduler enables threads to be grouped and a priority assigned to each group of threads. Round-robin order is maintained for each group. Consequently, the group priorities may be changed relatively frequently in order to obtain the benefits ... 08/10/06 - 20060179280 - Multithreading processor including thread scheduler based on instruction stall likelihood prediction An apparatus for scheduling dispatch of instructions among a plurality of threads being concurrently executed in a multithreading processor is provided. The apparatus includes an instruction decoder that generate register usage information for an instruction from each of the threads, a priority generator that generates a priority for each instruction ... 08/10/06 - 20060179279 - Bifurcated thread scheduler in a multithreading microprocessor A bifurcated instruction scheduler for dispatching instructions of multiple threads concurrently executing in a multithreading processor is provided. The scheduler includes a first portion within a reusable core that is not customizable by a customer, a second portion outside the core that is customizable, and an interface coupling the second ... 08/03/06 - 20060174091 - Instruction grouping history on fetch-side dispatch group formation An improved method, apparatus, and computer instructions for grouping instructions processed in equal sized sets. A current set of instructions is received in an instruction cache for dispatching. A determination is made as to whether any instructions in the current set of instructions are part of a group including a ... 07/13/06 - 20060155964 - Method and apparatus for enable/disable control of simd processor slices Methods and apparatus provide for disabling at least some data path processing circuits of a SIMD processing pipeline, in which the processing circuits are organized into a matrix of slices and stages, in response to one or more enable flags during a given cycle. ... 07/13/06 - 20060155963 - Assist thread for injecting cache memory in a microprocessor A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference ... 07/13/06 - 20060155962 - Processing activity masking in a data processing system Apparatus for processing data under control of data processing instructions specifying data processing operations, said apparatus comprising: a first execution mechanism operable to execute a first set of data processing instructions; a second execution mechanism operable to execute a second set of data processing instructions, said first set of data ... 05/04/06 - 20060095729 - Multithreaded processor with multiple concurrent pipelines per thread A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ... 05/04/06 - 20060095728 - Method and apparatus to provide a source operand for an instruction in a processor A method and apparatus for providing a source operand for an instruction to be executed in a processor. Some embodiments may include a register file unit that has registers and a scheduler to schedule instructions. In some embodiments, the scheduler is to asynchronously receive an instruction and a source operand ... 04/27/06 - 20060090061 - Continual flow processor pipeline Embodiments of the present invention relate to a system and method for comparatively increasing processor throughput and relieving pressure on the processor's scheduler and register file by diverting instructions dependent on long-latency operations from a flow of the processor pipeline and re-introducing them into the flow when the long-latency operations ... 02/16/06 - 20060036834 - Trace reuse A trace management architecture to enable the reuse of uops within one or more repeated traces. More particularly, embodiments of the invention relate to a technique to prevent multiple accesses to various functional units within a trace management architecture by reusing traces or sequences of traces that are repeated during ... 01/05/06 - 20060004989 - Mechanism for selecting instructions for execution in a multithreaded processor In one embodiment, a multithreaded processor includes a plurality of buffers, each configured to store instructions corresponding to a respective thread. The multithreaded processor also includes a pick unit coupled to the plurality of buffers. The pick unit may pick from at least one of the buffers in a given ... 12/15/05 - 20050278509 - Mechanism for eliminating the restart penalty when reissuing deferred instructions One embodiment of the present invention provides a system which facilitates eliminating a restart penalty when reissuing deferred instructions in a processor that supports speculative-execution. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, ... 11/10/05 - 20050251655 - Multi-scalar extension for simd instruction set processors A method is provided for executing a plurality of parallel executable sequences of instructions on a processor having a plurality of execution units operated by a single instruction unit. The method includes a) detecting a plurality of sequences of instructions adapted for parallel execution from instructions being provided to the ... 11/10/05 - 20050251654 - System and method of execution of register pointer instructions ahead of instruction issue A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides ... 10/06/05 - 20050223195 - Processor for making more efficient use of idling components and program conversion apparatus for the same A processor that has a plurality of instruction slots each of which stores an instruction to be executed in parallel. One of the plurality of instruction slots is a first instruction slot and another a second instruction slot. A special instruction stored in the first instruction slot is executed by ... 10/06/05 - 20050223194 - Method and structure for explicit software control using scoreboard status information A user is provided with means to sample memory hierarchy via software. This allows a user to enhance memory-level parallelism via software. A status of information needed for execution of a second computer program instruction is read in response to execution of a first computer program instruction. Execution continues with ... 10/06/05 - 20050223193 - Apparatus and method for control processing in dual path processor According to embodiments of the invention, there is disclosed a computer processor architecture; and in particular a computer processor, a method of operating the same, and a computer program product that makes use of an instruction set for the computer. In one embodiment according to the invention, there is provided ... 08/11/05 - 20050177704 - Processor for making more efficient use of idling components and program conversion apparatus for the same A processor that has a plurality of instruction slots each of which stores an instruction to be executed in parallel. One of the plurality of instruction slots is a first instruction slot and another a second instruction slot. A special instruction stored in the first instruction slot is executed by ... 07/07/05 - 20050149697 - Mechanism to exploit synchronization overhead to improve multithreaded performance Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and an event detector to detect a long latency event associated with a synchronization object. The event detector can ... ### FreshPatents.com Support |