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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Instruction Decoding (e.g., By Microinstruction, Start Address Generator, Hardwired) > Decoding Instruction To Accommodate Variable Length Instruction Or Operand Decoding Instruction To Accommodate Variable Length Instruction Or OperandDecoding Instruction To Accommodate Variable Length Instruction Or Operand patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.02/02/06 - 20060026392 - Method and system of informing a micro-sequence of operand width A method and system of informing a micro-sequence of operand width. At least some of the illustrative embodiments may be a method comprising fetching a first opcode, asserting a flag if the first opcode modifies an operand width of a subsequent opcode, fetching a second opcode, triggering a micro-sequence based ... 01/26/06 - 20060020772 - Method and apparatus for compressing and decompressing instructions in a computer system The apparatus and methods improve performance in a computer system by compressing a plurality of instructions having the same function with consecutively addressed operands and decompressing the compressed instruction by replicating the instruction with incremented operands. ... 12/29/05 - 20050289325 - Instruction set extension using operand bearing nop instructions Instruction set extension using operand bearing no-operation (NOP) or other instructions. In one embodiment, an apparatus can execute a first instruction with an operand associated with a second instruction. The apparatus includes a decoder to identify an operand associated with the second instruction as being designated for the first instruction. ... 12/15/05 - 20050278508 - Program instruction decompression and compression techniques A data processing system including an instruction cache 8 and an instruction decompression circuit 10 between the instruction cache 8 and a compressed instruction data memory 12. The instruction decompression circuit decompresses compressed instruction data CID recovered from the compressed instruction data memory and forms program instructions which are supplied ... 12/15/05 - 20050278507 - Long displacement instruction formats A computer architecture that provides the definition of a 20 bit signed displacement value used to form the operand storage address. ... 11/24/05 - 20050262329 - Processor architecture for executing two different fixed-length instruction sets A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible with a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or more 32-bit instructions. Switching between 16-bit instruction execution and 32-bit instruction execution is ... 09/08/05 - 20050198471 - Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes ... 09/08/05 - 20050198470 - Compression of program instructions using advanced sequential correlation Compressing program binaries with reduced compression ratios. One or several pre-processing acts are performed before performing compression using a local sequential correlation oriented compression technology such as PPM, or one of its variants or improvements. One pre-processing act splits the binaries into several substreams that have high local sequential correlation. ... 08/25/05 - 20050188179 - Apparatus and method for instruction-level specification of floating point format Apparatus and method are provided for extending a microprocessor instruction set to allow for instruction-level specification of floating point format to be employed during execution of an associated floating point operation. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro ... 08/04/05 - 20050172106 - Aliasing data processing registers A register data store 20 is provided within a data processing system 2. The register data store 20 may be accessed via registers for which a data processing instruction specifies a register size Q, D and a data element size S16, S8 for the multiple SIMD data elements to be ... 06/09/05 - 20050125633 - Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the Instructions of a program are stored in compressed form in a program memory (12). In a processor which executes the instructions, a program counter (50) identifies a position in the program memory. An instruction cache (40) has cache blocks, each for storing one or more instructions of the program in ... ### FreshPatents.com Support |