REGISTER now for FREE 
|
FREE patent keyword monitoring and additional FREE benefits. REGISTER now for FREE
|
|
|
Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Instruction Decoding (e.g., By Microinstruction, Start Address Generator, Hardwired) > Decoding Instruction To Accommodate Plural Instruction Interpretations (e.g., Different Dialects, Languages, Emulation, Etc.) Decoding Instruction To Accommodate Plural Instruction Interpretations (e.g., Different Dialects, Languages, Emulation, Etc.)Decoding Instruction To Accommodate Plural Instruction Interpretations (e.g., Different Dialects, Languages, Emulation, Etc.) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236077 - Microprocessor access of operand stack as a register file using native instructions A combined native (RISC or CISC) microprocessor and stack (Java) machine are constructed so that Java VM instructions can be executed in hardware. Most Java instructions are executed directly, while more complex Java instructions, such as those manipulating Java objects, are executed as native microcode. In order for native microcode ... 10/05/06 - 20060224861 - Condition branch instruction encoding within a multiple instruction set data processing system A data processing system is operable in a first state to use a first instruction set having a first instruction set encoding. The data processing system is also operable in a second state to use a second instruction set having a second instruction encoding. Conditional branch instructions provided within the ... 09/28/06 - 20060218379 - Method and system for encoding variable length packets with variable instruction sizes Techniques for processing transmissions in a communications (e.g., CDMA) system. The method and system encode and process instructions of mixed lengths (e.g., 16 bits and 32 bits) and instruction packets including instructions of mixed lengths. This includes encoding a plurality of instructions of a first length and a plurality of ... 08/10/06 - 20060179278 - Methods and apparatus for instruction set emulation Methods and apparatus provide for translating a software program page by page from a first instruction set architecture (ISA) into a second ISA using one or more of a set of processors of a multi-processor system; and executing the translated software program using a dedicated other processor of the multi-processor ... 06/29/06 - 20060143429 - Method for executing plural programs, method for converting source programs and compiler program using these methods A synchronous reference code indicative of the fact that synchronous updating was made is provided to data which is to be applied to a critical section, and the code is set when synchronous updating is made. After a sentence in the critical section is executed, it is confirmed whether or ... 05/11/06 - 20060101240 - Digital signal processing circuit and digital signal processing method According to an aspect of the present invention, there is provided with a digital signal processing circuit, including: an instruction memory which outputs an instruction code containing at least one instruction and a selection code; an extended-instruction storage which stores extended instructions; a selector which selects, from the extended-instruction storage, ... 05/04/06 - 20060095727 - Information processing device and information processing method An information processing device for sequentially reading and executing programs stored in memory means, including: a program counter for outputting an address for reading a program to the memory means; an instruction decoder for decoding instructions read from the memory means in response to a control signal indicating a period ... 02/02/06 - 20060026391 - Automatic operand load and store A processor that comprises decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in ... 01/19/06 - 20060015704 - Operation apparatus and instruction code executing method An operation apparatus includes signal lines, a decoder connected with the signal lines and configured to sequentially decode first and second instruction codes on the signal lines, an instruction executing section configured to execute operation processing based on each of the decoding results of the first and second instruction codes ... 11/10/05 - 20050251653 - System and method for translating non-native instructions to native instructions for processing on a host processor A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts ... 11/10/05 - 20050251652 - Methods and apparatus for processing an extensible firmware interface byte code instruction in a loop Methods and apparatus to process a virtual machine instruction in a loop are described herein. In an example method, at least one of a loop-start instruction and a loop-end instruction associated with a loop having the virtual machine instruction is monitored. In response to detecting the loop-start instruction, the virtual ... 10/06/05 - 20050223192 - Instruction sets for processors A first operation (add) is specifiable in both the first and second external formats (F1, F2) and a second operation (load) is specifiable in the second external format (F2). The first and second operations have distinct opcodes (101, 011) in the second external format. In each of the preselected opcode ... 09/29/05 - 20050216704 - Device and method for managing a microprocessor instruction set A microprocessor has a set of determined instructions which are coded on a determined number P of bits in an instruction coding space of size 2{circumflex over ( )}P. The microprocessor includes a mode register having a determined number N of mode bits. A further included decoding unit and an execution ... 06/23/05 - 20050138330 - Maxq microcontroller A microcontroller includes a program memory, data memory, central processing unit, at least one register module, a memory management unit, and a transport network. Instructions are executed in one clock cycle via an instruction word. The instruction word indicates the source module from which data is to be retrieved and ... ### FreshPatents.com Support |