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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Instruction Fetching Instruction FetchingInstruction Fetching patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/14/06 - 20060206691 - Memory organization allowing single cycle pointer addressing where the address of the pointer is also contained in one of the memory locations All Pointer-based accesses require first that the value contained in a pointer register (200a, 200b, 200c, 200d) to be read and then that value be used as an address to the appropriate region in random access memory (RAM) (104). As implemented today, this requires two memory read access cycles, each ... 08/10/06 - 20060179276 - Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetch instructions. The fetch director includes a circuit for ... 08/10/06 - 20060179275 - Methods and apparatus for processing instructions in a multi-processor system Methods and apparatus provide for transferring blocks of data between a shared memory and one or more of a plurality of parallel processors, each processor including a local memory; executing one or more programs within the local memory of one or more of the processors, wherein the one or more ... 08/10/06 - 20060179274 - Instruction/skid buffers in a multithreading microprocessor An apparatus for reducing instruction re-fetching in a multithreading processor configured to concurrently execute a plurality of threads is disclosed. The apparatus includes a buffer for each thread that stores fetched instructions of the thread, having an indicator for indicating which of the fetched instructions in the buffer have already ... 06/22/06 - 20060136701 - System and program to automatically identify a server on which to deploy an application A system, method and computer program product for determining one of a plurality of servers on which to install and execute an application. First program instructions obtain information from each of the plurality of servers as to amounts of availability of their respective CPUs, RAMs and storage. Second program instructions ... 06/01/06 - 20060117166 - Coprocessor instruction loading from port register based on interrupt vector table indication A coprocessor interface is described which provides a flexible degree of coupling with a host control processor. Specific methods are defined for architectures to make use of the interface for supporting client-server coprocessors (CSCOPs). A dynamic debug interface is used to provide a coprocessor interface which supports tightly coupled, loosely ... 05/04/06 - 20060095726 - Independent hardware based code locator A hardware code relocator compiles code and executes starting at any address in memory. A hardware mechanism external to a CPU re-directs an instruction to the appropriate physical location in memory by adding a vector base offset to a fetch address and retrieving the instruction based upon a new fetch ... 05/04/06 - 20060095725 - Method and apparatus for executing instructions from an auxiliary data stream System and method for the execution of instructions from an auxiliary data stream in a parallel processing system are presented. The data processing system includes a program sequencer, an array processor and data input/output logic. Rather than increasing the program memory size to accommodate the most extreme application requirements, a ... 02/09/06 - 20060031661 - Processor for executing instructions in units that are unrelated to the units in wihcih instructions are read,and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor When a branch instruction is decoded by the instruction decoders 409a-409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator ... 11/24/05 - 20050262328 - Processor and method for processing vliw instructions Described are a processor device and a method for processing instructions, in particular VLIW instructions, wherein instruction words are stored in a memory means, each instruction word consisting of segments, the instruction words are fetched from the memory means, and instructions are executed in accordance with instruction words fetched from ... 11/10/05 - 20050251651 - Microcomputer and dividing circuit Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having ... 08/11/05 - 20050177703 - Thread id in a multithreaded processor A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or ... 06/23/05 - 20050138328 - Across-thread out of order instruction dispatch in a multithreaded graphics processor Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions are fetched into an instruction buffer that is configured to store an instruction from each of the threads. A dispatch circuit determines which instructions in the buffer are ready ... ### FreshPatents.com Support |