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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Architecture > Microprocessor Or Multichip Or Multimodule Processor Having Sequential Program Control > Including Coprocessor Including CoprocessorIncluding Coprocessor patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/07/06 - 20060200647 - Packet processor with wide register set architecture A Wide Register Set (WRS) is used in a packet processor to increase performance for certain packet processing operations. The registers in the WRS have wider bit lengths than the main registers used for primary packet processing operations. A wide logic unit is configured to conduct logic operations on the ... 08/10/06 - 20060179273 - Data processor adapted for efficient digital signal processing and method therefor A data processor (200) includes a processor core (300), an interface (210) coupled to the processor core (210), and a coprocessor (500). The coprocessor (500) is coupled to the processor core (300) via the interface (210) and includes a first list memory (522). In response to a predetermined instruction the ... 07/13/06 - 20060155959 - Method and apparatus to provide efficient communication between processing elements in a processor unit A context forwarding bus efficiently communicates control and data between processing elements in a processor unit having a plurality of processing elements. Control and data information is transferred over a first bus from processing element to processing element. ... 05/11/06 - 20060101236 - Method and apparatus for increasing processing speed using quantum coprocessor A method and apparatus for increasing a processing speed using a quantum coprocessor are provided. The method includes receiving a command and data for performing a predetermined task, converting the command and the data into a signal having a format that the quantum coprocessor can receive if the command requests ... 05/04/06 - 20060095723 - Method and apparatus for interfacing a processor to a coprocessor A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register ... 05/04/06 - 20060095722 - Program subgraph identification There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within said program, said apparatus comprising: a memory operable to store a program formed of separate program instructions; processing ... 05/04/06 - 20060095721 - Tightly coupled accelerator An accelerator 120 is tightly coupled to the normal execution unit 110. The operand store, which could be a register file 130, a stack based operand store or other operand store is shared by the execution unit and the accelerator unit. Operands may also be accessed as immediate values within ... 05/04/06 - 20060095720 - Reuseable configuration data There is provided an information processor for executing a program comprising a plurality of separate program instructions: processing logic operable to individually execute said separate program instructions of said program; an operand store operable to store operand values; and an accelerator having an array comprising a plurality of functional units, ... 05/04/06 - 20060095719 - Microcontroller having partial-twin structure A partial twin microprocessor structure which can run multiple tasks in parallel is disclosed. The partial-twin microprocessor structure comprises a first set of processing units to be shared by at least two tasks running in parallel, a plurality of program counters to store a plurality of program addresses for different ... 05/04/06 - 20060095718 - System and method for providing a persistent function server A system and method for providing a persistent function server is provided. A multi-processor environment uses an interface definition language (idl) file to describe a particular function, such as an “add” function. A compiler uses the idl file to generate source code for use in marshalling and de-marshalling data between ... 01/26/06 - 20060020771 - Parallel computer having a hierarchy structure In a multiprocessor system of a hierarchy configuration as a parallel computer of a common-bus structure, a processing unit (120) in an intermediate stage has a processor (123) having a programmable function that is equal to a normal processor, an instruction memory (125), and a data memory (127). The processing ... 01/19/06 - 20060015703 - Programmable processor architecture One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than ... 01/12/06 - 20060010305 - Processor system that controls data transfer between processor and coprocessor A processor system includes a main processor having registers and an instruction decode control unit, and a coprocessor. When the main processor performs an operation in accordance with an instruction, the registers store data to be used for the operation and data obtained by the operation, and the control unit ... 01/05/06 - 20060004987 - System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor ... 12/15/05 - 20050278504 - System capable of dynamically arranging coprocessor number A system capable of dynamically arranging coprocessor number, which uses a coprocessor instruction to be an instruction between a master processor and one or more coprocessors. The system includes plural coprocessors and a master processor. The plural coprocessors help the master processor to perform additional operations. The master processor executes ... 12/15/05 - 20050278503 - Coprocessor bus architecture According to some embodiments, a coprocessor bus architecture is provided. ... 12/15/05 - 20050278502 - Method and apparatus for chaining multiple independent hardware acceleration operations Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can be reduced by chaining multiple independent hardware acceleration operations within a circuit card assembly. Multiple ... 12/01/05 - 20050268072 - Apparatus and method for interconnecting a processor to co-processors using shared memory An apparatus and method for interfacing a processor to one or more co-processors interface provides a dual ported memory to be used as a message passing buffer between the processor and the co-processors. Both the processor and co-processors can connect asynchronously to the dual ported memory. Control logic monitors activity ... 09/29/05 - 20050216701 - Automatic configuration of a microprocessor A method for automatically configuring a microprocessor architecture so that it is able to efficiently exploit instruction level parallelism in a particular application. Executable code for another microprocessor type is translated into the specialised instruction set of the configured microprocessor. The configured microprocessor may then be used as a coprocessor ... 08/04/05 - 20050172104 - Method for transferring data in a multiprocessor system, multiprocessor system and processor carrying out this method The present invention relates to a data transfer method of a delegating processor (200), requiring the execution of functions, to a delegate processor (202), that executes these functions based on a function identifier and execution parameters associated with this function, this identifier and these parameters being provided by the delegating ... 07/28/05 - 20050166036 - Microcontroller instruction set An instruction set is provided that features multiple instructions and various address modes to deliver a mixture of flexible microcontroller-like instructions and specialized digital signal processing (“DSP”) execute instructions from a single instruction stream. A subset of instructions of the instruction set can be executed by a processor. Similarly, another ... 07/07/05 - 20050149693 - Methods and apparatus for dual-use coprocessing/debug interface A coprocessor interface is described which provides a flexible degree of coupling with a host control processor. Specific methods are defined for architectures to make use of the interface for supporting client-server coprocessors (CSCOPs). A dynamic debug interface is used to provide a coprocessor interface which supports tightly coupled, loosely ... 06/02/05 - 20050120190 - Hardware assisted communication between processors A method and apparatus performs hardware assisted communication between processors. In response to direction from a first processor, a first coprocessor writes information in a first block of mirrored memory. Mirrored memory is maintained, allowing a second coprocessor to read the information from a second block of mirrored memory. The ... ### FreshPatents.com Support |