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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Architecture > Long Instruction Word Long Instruction WordLong Instruction Word patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236076 - Method and apparatus for packing data An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed ... 10/12/06 - 20060230253 - Unified non-partitioned register files for a digital signal processor operating in an interleaved multi-threaded environment A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer can support very long instruction word (VLIW) instructions and superscalar instructions. The processor device further includes a first instruction execution unit responsive to the sequencer, a second instruction execution unit ... 08/03/06 - 20060174089 - Method and apparatus for embedding wide instruction words in a fixed-length instruction set architecture A method, system, and computer program product for mixing of conventional and augmented instructions within an instruction stream, wherein control may be directly transferred, without operating system intervention, between one type of instruction to another. Extra instruction word bits are added in a manner that is designed to minimally interfere ... 07/27/06 - 20060168424 - Processing apparatus, processing method and compiler Differences in encoding efficiency of instructions may arise if certain operations require very large immediate values as operands, as opposed to others requiring no immediate values or small immediate values. The present invention describes a processing apparatus, a compiler as well as a method for processing data, allowing the use ... 07/13/06 - 20060155958 - Processor architecture A LIW processor comprises multiple execution units. The multiple execution units of the processor are divided into groups, and an input instruction word can contain instructions for one execution unit in each of the groups. The processor is optimised for use in signal processing operations, in that the multiple execution ... 07/13/06 - 20060155957 - Encoding method for very long instruction word (vliw) dsp processor and decoding method thereof An encoding method for a very long instruction word (VLIW) DSP processor and decoding method thereof. The encoding method involves a plurality of first encoding portions and a plurality of second encoding portions. The first encoding portions and second encoding portions are complied from an instruction. The first encoding portions ... 07/06/06 - 20060149926 - Control words for instruction packets of processors and methods thereof Control words are included in instruction packets to influence how one or more instructions in the packet are executed. Whether the control word is short or long will depend upon the situation. A short control word will be included in the packet in the event that the short control word ... 05/04/06 - 20060095717 - Processor having compound instruction and operation formats A processor comprises a memory, an instruction decoder coupled to the memory for decoding instructions retrieved therefrom, and a plurality of execution units for executing the decoded instructions. One or more of the instructions are in a compound instruction format in which a single instruction comprises multiple operation fields, with ... 05/04/06 - 20060095716 - Super-reconfigurable fabric architecture (surfa): a multi-fpga parallel processing architecture for cots hybrid computing framework A field programmable gate array includes a virtual bus interface that receives a control word from a host processor over a standard I/O bus. A configurable very long instruction word (VLIW) controller receives the control word via virtual bus interface signals mapped from the virtual bus interface. A reconfigurable communication ... 05/04/06 - 20060095715 - Very long instruction word processor The invention relates to a very long instruction word (VLIW) processor comprising a plurality of functional units (110, 130, 135), each for executing an operation, and a VLIW controller (100) connected to each of said functional units (110, 130, 135) and adapted to controlling said functional units (110, 130, 135). ... 02/02/06 - 20060026388 - Computer executing instructions having embedded synchronization points A computer operable to execute instructions having embedded synchronization points includes a first program counter and a second program counter. The computer also includes a synchronization unit electrically coupled to the first and second program counters. When a synchronization point is reached, the synchronization unit is operable to stall the ... 01/05/06 - 20060004986 - Data processing apparatus address range dependent parallelization of instructions A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. ... 11/17/05 - 20050257028 - Program instruction compression A processor is described including a plurality of data path elements 2, 4, 6, 8 which independently perform in parallel different data processing operations. Program instructions are provided which are decoded to generate control signals for controlling the data path elements. Multiple instruction sets are supported with the same data ... 11/17/05 - 20050257027 - Processing apparatus, processing method and compiler Computer architectures consist of a fixed data path, which is controlled by a set of control words. Each control word controls part of the data path. Each set of instructions generates a new set of control words. In case of a VLIW processor, multiple instructions are packaged into one so-called ... 11/03/05 - 20050246515 - Method for the coding/decoding of vliw cached instructions A method for controlling functional units in a processor is provided. During a configuration phase of the processor, a series of primary instruction words from the translation of a programme code are subjected to a division into series of instruction word bits. By this, the instruction words controlling the processor ... 10/13/05 - 20050228969 - Process for delivering very long instruction words to a processor and integrated circuit with an associated program memory device An integrated circuit includes a processor and a program memory device on a common substrate. The memory device is able to deliver to the processor VLIW instructions with at least m operative fields. The memory device comprises: a dictionary memory comprising dictionary instructions each having at least m dictionary elementary ... 08/18/05 - 20050182916 - Processor and compiler A VLIW processor which has an instruction set whose size is reduced so that a small number of bits are necessary to specify registers is provided. The VLIW processor 10 comprises the register file 12, the first-the third operation units 14a-14c and the like, and executes the very long instruction ... 06/23/05 - 20050138327 - Vliw digital signal processor for achieving improved binary translation A VLIW digital signal processor is composed of a program memory including first to n-th banks, first to n-th address counters, a fetch block, and an instruction executing section. The first to n-th banks store therein first to n-th programs, respectively. The first to n-th address counters respectively indicates addresses ... ### FreshPatents.com Support |