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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Architecture > Array Processor > Array Processor Element Interconnection Array Processor Element InterconnectionArray Processor Element Interconnection patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/28/06 - 20060218376 - Methods and apparatus for efficiently sharing memory and processing in a multi-processor A shared memory network for communicating between processors using store and load instructions is described. A new processor architecture which may be used with the shared memory network is also described that uses arithmetic/logic instructions that do not specify any source operand addresses or target operand addresses. The source operands ... 09/21/06 - 20060212678 - Reconfigurable processor array exploiting ilp and tlp A processing system according to the invention comprises a plurality of processing elements, and the plurality of processing elements comprises a first set of processing elements and at least a second set of processing elements. Each processing element of the first set comprises a register file and at least one ... 09/07/06 - 20060200646 - Data processing system with clustered ilp processor The invention is based on the idea to specify operations from different cycles in one instruction and, consequently, to pipeline control connections to remote clusters. Therefore a data processing system is provided. Said system comprises a clustered ILP processor having a plurality of clusters each comprising at least one register ... 08/10/06 - 20060179272 - Data processing system, method and interconnect fabric for partial response accumulation in a data processing system A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to ... 08/10/06 - 20060179271 - Bisectional fault detection system An apparatus, program product and method logically divides a group of nodes and causes node pairs comprising a node from each section to communicate. Results from the communications may be analyzed to determine performance characteristics, such as bandwidth and proper connectivity. ... 08/10/06 - 20060179270 - All row, planar fault detection system An apparatus, program product and method for detecting nodal faults may simultaneously cause designated nodes of a cell to communicate with all nodes adjacent to each of the designated nodes. Furthermore, all nodes along the axes of the designated nodes are made to communicate with their adjacent nodes, and the ... 08/10/06 - 20060179269 - Multi-directional fault detection system An apparatus, program product and method checks for nodal faults in a group of nodes comprising a center node and all adjacent nodes. The center node concurrently communicates with the immediately adjacent nodes in three dimensions. The communications are analyzed to determine a presence of a faulty node or connection. ... 08/10/06 - 20060179268 - Row fault detection system An apparatus, program product and method checks for nodal faults in a row of nodes by causing each node in the row to concurrently communicate with its adjacent neighbor nodes in the row. The communications are analyzed to determine a presence of a faulty node or connection. ... 08/10/06 - 20060179267 - Method and structure for skewed block-cyclic distribution of lower-dimensional data arrays in higher-dimensional processor grids A method and structure of distributing elements of an array of data in a computer memory to a specific processor of a multi-dimensional mesh of parallel processors includes designating a distribution of elements of at least a portion of the array to be executed by specific processors in the multi-dimensional ... 07/27/06 - 20060168423 - Array synchronisation A method is disclosed for achieving synchronization in an array of semi-synchronous devices. A processor array has an array of processor elements, wherein each of said processor elements comprises a cycle counter, and a master processor element is able to transmit control command signals to each of the other processor ... 07/13/06 - 20060155956 - Processor array There is disclosed a processor array, which achieves an approximately constant latency. Communications to and from the farthest array elements are suitably pipelined for the distance, while communications to and from closer array elements are deliberately “over-pipelined” such that the latency to all end-point elements is the same number of ... 07/06/06 - 20060149923 - Microprocessor optimized for algorithmic processing Provided is a microprocessor optimized for algorithmic processing for accelerating algorithm processing through a closely coupled set of parallel sub-processing elements. The device includes a primary processor, one or more subprocessors and an interconnecting buss. The buss is preferably a crossbar buss. The primary processor is preferably a pipelined CPU ... 05/11/06 - 20060101234 - Systems and methods of balancing crossbar bandwidth Systems and methods of balancing crossbar bandwidth in a multiprocessing system are disclosed. In an exemplary embodiment a system may comprise a crossbar switch having a plurality of links to processors in the multiprocessing system. A plurality of synchronizers is provided to receive micropackets from the links. At least one ... 05/11/06 - 20060101233 - Clustered instruction level parallelism processor The basic idea of the invention is to provide a clustered ILP processor based on a fully-connected inter-cluster network with a non-uniform latency. A clustered Instruction Level Parallelism processor is provided. Said processor comprises a plurality of clusters (C1-C6) each comprising at least one register file (RF) and at least ... 02/09/06 - 20060031659 - Multi-processor reconfigurable computing system A reconfigurable multi-processor computing system including a plurality of configurable processing elements each having a plurality of integrated high-speed serial input/output ports. Interconnects link the plurality of processing elements, wherein at least one of the integrated high-speed serial input/output ports of each processing element is connected by at least one ... 01/19/06 - 20060015701 - Arithmetic node including general digital signal processing functions for an adaptive computing machine An apparatus for processing operations in an adaptive computing environment is provided. The adaptive computing environment including at least one processing node. A node includes a memory configured to receive and store data. The data is received from a programmable interconnection network and stored. The node also includes an execution ... 11/17/05 - 20050257024 - Loosely-biased heterogeneous reconfigurable arrays A heterogeneous array includes clusters of processing elements. The clusters include a combination of ALUs and multiplexers linked by direct connections and various general-purpose routing networks. The multiplexers are controlled by the ALUs in the same cluster, or alternatively by ALUs in other clusters, via a special purpose routing network. ... 09/29/05 - 20050216699 - Parallel operation processor A processor having a plurality of processing elements and a decoder operable to decode an instruction. Each of the plurality of processing elements includes: a transfer pattern storage unit operable to store a transfer pattern value that indicates a processing element from which data is transferred; a transfer unit operable ... 07/28/05 - 20050166033 - System and method using embedded microprocessor as a node in an adaptable computing machine The present invention provides an adaptive computing engine (ACE) that includes processing nodes having different capabilities such as arithmetic nodes, bit-manipulation nodes, finite state machine nodes, input/output nodes and a programmable scalar node (PSN). In accordance with one embodiment of the present invention, a common architecture is adaptable to function ... 07/14/05 - 20050154858 - Configurable bi-directional bus for communicating between autonomous units Processing units (PUs) are coupled with a gated bi-directional bus structure that allows the PUs to be cascaded. Each PUn has communication logic and function logic. Each PUn is physically coupled to two other PUs, a PUp and a PUf. The communication logic receives Link Out data from a PUp ... 07/14/05 - 20050154857 - Data processing system The invention relates to a processing system comprising a calculation device comprising at least one calculation unit (13), a storage device and a system for switching between the storage device and the calculation device. In order to reduce the size of the switching system, the storage device comprises several banks ... 07/07/05 - 20050149692 - Multiprocessor data processing system having scalable data interconnect and data routing mechanism The data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one application, a data processing system includes first and second processing books, each including at least first and second ... 07/07/05 - 20050149691 - Processing element with next and previous neighbor registers According to some embodiments, a processing element includes (i) a next neighbor register to receive information directly from a previous processing element in a series of processing elements, and (ii) a previous neighbor register to receive information directly from a next processing element in the series. ... 06/23/05 - 20050138325 - Multi-chip module with third dimension interconnect A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which ... 06/16/05 - 20050132163 - Method and system of interconnecting processors of a parallel computer to facilitate torus partitioning The present invention provides a method and system of interconnecting L processors of a parallel computer to facilitate torus partitioning, (a) where each of the processors includes a processing unit and a switch, (b) where the switch includes a first external port, a second external port, a third external port, ... ### FreshPatents.com Support |