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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Architecture > Array Processor Array ProcessorArray Processor patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/28/06 - 20060218375 - System and method of transferring data between a massive number of processors This present invention brings to the multiprocessor what vectorization brought to the single processor. It provides similar tools to speed communication that have traditionally been used to speed computation; namely, the capability to program optimal communication algorithms on an architecture that can replicate their performance in terms of wall clock ... 07/13/06 - 20060155955 - Simd-risc processor module A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which ... 07/06/06 - 20060149922 - Multiple computational clusters in processors and methods thereof A processor may have more than one computational cluster. An instruction packet may include an instruction replication control word to indicate that a particular machine language instruction in the instruction packet is to be executed in parallel by two or more of the computational clusters. An instruction packet may include ... 07/06/06 - 20060149921 - Method and apparatus for sharing control components across multiple processing elements Method and apparatus for sharing control components across multiple processing elements. In one embodiment, common control components, including a control store and instruction control unit, are shared across multiple processing cores on a combined microengine. Each processing core includes a respective datapath and register file. Instruction gating logic is employed ... 06/29/06 - 20060143428 - Semiconductor signal processing device An orthogonal memory for transforming arrangements of system bus data and processing data is placed between a system bus interface and a memory cell mat storing the processing data. The orthogonal memory includes two-port memory cells, and changes data train transferred in a bit parallel and word serial fashion into ... 05/25/06 - 20060112258 - Parallel data path architecture for high energy efficiency Provided is a parallel data path architecture for high energy efficiency. In this architecture, a plurality of parallel process units and a plurality of function units of the process units are controlled by instructions and processed in parallel to improve performance. Also, since only necessary process units and function units ... 05/11/06 - 20060101232 - Semiconductor integrated circuit There are provided dedicated cell groups 1304, 1306 for executing memory access processing to built-in memories 1313, 1312 in a plurality of ALU cells. Further there are provided dedicated cell groups 1304, 1306 enabling access commonly available for built-in memories to a peripheral circuit 1201 or LSI external device 206. ... 05/11/06 - 20060101231 - Semiconductor signal processing device An instruction for an arithmetic/logic operation to a main processing circuit is stored in the form of a micro program in a micro instruction memory, and the operation of the main processing circuit is controlled in accordance with the micro program, under the control of a controller. In the main ... 11/10/05 - 20050251646 - Network with programmable interconnect nodes adapted to large integrated circuits A circuit having an interconnect network and plurality of processing blocks is disclosed. The interconnect network has a plurality of network nodes arranged in a two-dimensional array on a first substrate. Each network node has a plurality of communication ports and is connected to each adjacent network node by a ... 10/20/05 - 20050235134 - Apparatus, method and system for a synchronicity independent, resource delegating, power and instruction optimizing processor An apparatus, method, and system for synchronicity independent, resource delegating, power and instruction optimizing processor is provided where instructions are delegated between various processing resources of the processor. An Integer Processing Unit (IPU) of the processor delegates complicated mathematical instructions to a Mathematical Processing Unit (MPU) of the processor. Furthermore, ... 08/18/05 - 20050182915 - Chip multiprocessor for media applications A chip multiprocessor (CMP) includes a plurality of processors disposed on a peripheral region of a chip. Each processor has (a) a dual datapath for executing instructions, (b) a compiler controlled register file (RF), coupled to the dual datapath, for loading/storing operands of an instruction, and (c) a compiler controlled ... 08/04/05 - 20050172103 - Array-type computer processor An array-type computer processor obtains data of a predetermined number of cooperative partial instruction codes, and operates with temporarily holding only a predetermined number of data-obtained instruction codes, from an external program memory which stores data of a computer program. Every time the operations with the temporarily-held instruction codes are ... 08/04/05 - 20050172102 - Array-type computer processor An array-type computer processor stops, with a plurality of computer programs held, a state control unit and a data-path unit, upon input of event data for task switching. The array-type computer processor obtains the operation state of the state control unit and the processed data of the data-path unit when ... 06/23/05 - 20050138324 - Processing unit having a dual channel bus architecture A processing unit having a dual channel bus architecture associated with a specific instruction set, configured to receive an input message and transmit an output message that is identical or derived therefrom. A message consists of one opcode, with or without associated data, used to control each processing unit depending ... ### FreshPatents.com Support |