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Electrical Computers And Digital Processing Systems: Memory > Address Formation > Address Mapping (e.g., Conversion, Translation) > Virtual Addressing > Translation Tables (e.g., Segment And Page Table Or Map) > Directory Tables (e.g., Dlat, Tlb) Directory Tables (e.g., Dlat, Tlb)Directory Tables (e.g., Dlat, Tlb) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.07/27/06 - 20060168422 - System for indicating a plug position for a memory module in a memory system A memory system including a first and second of set of socket pads adapted for connection to memory module continuity pins. The memory system also includes a first indicator corresponding to the first set of socket pads. The memory system also includes a second indicator corresponding to the second set ... 04/20/06 - 20060085624 - Data processing apparatus and method A data processing apparatus and method are capable of facilitating maintenance, such as debugging, provision of additional functions and the like, by adopting, as separate modules, a unit for fetching data from a database upon receipt of a request to output the data from a client, and a unit for ... 03/23/06 - 20060064567 - Translating loads for accelerating virtualized partition A system, which includes a processor that includes a plurality of cores, generates an address translation when there is a miss in a translation lookaside buffer (TLB). A hypervisor utilizes a translating load instruction that upon execution on the processor generates a data portion of a TLB entry. Execution of ... 03/02/06 - 20060047936 - System and method for using address lines to control memory usage A computing environment maintains the integrity of data stored in system memory. The system has a memory management unit that maintains a plurality of real page numbers. The system also comprises an address bus in communication with the memory management unit. The address bus comprises a plurality of address lines, ... 03/02/06 - 20060047935 - Data processing system having translation lookaside buffer valid bits with lock and method therefor A system (10) translates memory addresses. Processing circuitry (12) provides an effective address to a storage array (14, 16) having a plurality of stored effective addresses, each of the plurality of stored effective addresses having a corresponding pair of a lock bit and a valid bit. An output tag value ... 02/02/06 - 20060026383 - Method for efficient virtualization of physical memory in a virtual-machine monitor Various embodiments of the present invention are directed to efficient provision, by a virtual-machine monitor, of a virtual, physical memory interface to guest operating systems and other programs and routines interfacing to a computer system through a virtual-machine interface. In one embodiment of the present invention, a virtual-machine monitor maintains ... 02/02/06 - 20060026382 - Information processor and multi-hit control method The present invention comprises, for enabling sharing an address translation buffer (TLB=Translation Lookaside Buffer) between plural threads without generating undesirable multi-hits in an information processor which operates in multi-thread mode, an address translation buffer for storing address translation pairs and thread information, a retriever for retrieving an address translation pair ... 02/02/06 - 20060026381 - Address translation information storing apparatus and address translation information storing method Context information pertaining to the virtual address is obtained, and a storage location for storing the address translation information is determined based on the context information. ... 02/02/06 - 20060026380 - Apparatus and method for controlling address conversion buffer A method for controlling an address conversion buffer, constituted on a processor capable of executing a plurality of threads simultaneously on one core, includes registering address conversion information in an entry of the address conversion buffer that includes a first memory area usable by one of the threads and a ... 12/08/05 - 20050273575 - Mechanism to invalidate data translation buffer entries a multiprocessor system According to one embodiment a computer system is disclosed. The computer system includes a first central processing unit (CPU) having a translation buffer (TB) to store virtual to physical address translations, and a snoop filter coupled to the first CPU to mirror the operation of the first TB and implemented ... 12/08/05 - 20050273574 - Method of determining whether a virtual address corresponds to a physical address in a translation lookaside buffer A method of determining whether a virtual address corresponds to a physical address in a translation lookaside buffer (TLB) includes receiving a virtual address, setting the page type of the virtual address according to a rank of the page types, picking index bits and tag compared address from the virtual ... 10/27/05 - 20050240751 - Virtual translation lookaside buffer In one embodiment, a method for supporting address translation in a virtual-machine environment includes creating a guest translation data structure to be used by a guest operating system for address translation operations, creating an active translation data structure based on the guest translation data structure, and periodically modifying the content ... 09/08/05 - 20050198466 - Partial address compares stored in translation lookaside buffer A method of performing a fast information compare within a processor which includes performing a more significant bit compare when information is loaded into a translation lookaside buffer, storing a result of the more significant bit compare within the translation lookaside buffer as part of an entry containing the information, ... 08/18/05 - 20050182913 - Option rom virtualization A method and system for virtualizing images. Multiple images are shadowed (i.e., copied) into portions of the physical address space of system memory. A mapping mechanism is effected to map all of the images into a common virtual address space, wherein images in the virtual address space are overlapped, thus ... 08/04/05 - 20050172099 - Method and apparatus for memory management in a multi-processor computer system Improved techniques and systems for accommodating TLB shootdown events in multi-processor computer systems are disclosed. A memory management unit (MMU) having a TLB miss handler and miss exception handler is provided. The MMU receives instructions relative to a virtual address. A TLB is searched for the virtual address, if the ... 07/21/05 - 20050160250 - Method and apparatus of controlling electric power for translation lookaside buffer The present invention is intended to reduce unnecessary power consumption by controlling disconnection of entries unused in a translation lookaside buffer (TLB) for a long time. In an aspect of the present invention, there is provided a method of controlling electric power consumed for a translation lookaside buffer (TLB) within ... ### FreshPatents.com Support |