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Electrical Computers And Digital Processing Systems: Memory > Address Formation > Address Mapping (e.g., Conversion, Translation) > Virtual Addressing > Translation Tables (e.g., Segment And Page Table Or Map) Translation Tables (e.g., Segment And Page Table Or Map)Translation Tables (e.g., Segment And Page Table Or Map) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236072 - Memory hashing for stride access An apparatus and method in a computer system allows a software application to specify an intended stride access when writing data elements into a memory. A memory control in the computer system writes data in a manner that provides improved access performance when accesses to the data elements are performed ... 09/14/06 - 20060206687 - Method and system for a second level address translation in a virtual machine environment A method of performing a translation from a guest virtual address to a host physical address in a virtual machine environment includes receiving a guest virtual address from a host computer executing a guest virtual machine program and using the hardware oriented method of the host CPU to determine the ... 07/06/06 - 20060149919 - Method, system, and program for addressing pages of memory by an i/o device Provided are a method, system, and program for translating virtual addresses of memory locations within pages of different sizes. In one embodiment, a translation entry containing a physical address is stored in a data structure table for each page. Each virtual address includes a page virtual address which identifies the ... 06/22/06 - 20060136697 - Method, system, and program for updating a cached data structure table Provided are a method, system, and program for updating a cache in which, in one aspect of the description provided herein, changes to data structure entries in the cache are selectively written back to the source data structure table maintained in the host memory. In one embodiment, translation and protection ... 06/22/06 - 20060136696 - Method and apparatus for address translation A memory management unit (MMU) has a cache for storing address translation entries (ATEs) corresponding to virtual addresses. If an ATE is present for a requested virtual address, then it is translated to the physical address and sent to main memory. If the MMU cache misses, the virtual address is ... 06/15/06 - 20060129786 - Methods and apparatus for address translation from an external device to a memory of a processor Methods and apparatus provide for using a first portion of an external address as a pointer to select one of a plurality of entries in a segment table, each entry of the segment table representing a different segment of a memory; using at least a portion of the selected entry ... 05/18/06 - 20060107023 - Sparse table compaction method A method and system of sparse table compaction is disclosed. A repeating data pattern may be detected in a large data structure, identifying the large data structure as a sparse table. The large data structure is stored in a virtual memory as a series of virtual data pages. Multiple repeating ... 05/18/06 - 20060107022 - Methods and structure for bypassing memory management mapping and translation features Methods and associated structures for bypassing virtual memory and memory mapping management features provided in a memory controller applied to simpler computing applications. In one aspect hereof, simpler, embedded computing applications may utilize standard memory controllers including cash management and memory component interfacing features but may bypass virtual memory management ... 03/30/06 - 20060069899 - Performance enhancement of address translation using translation tables covering large address spaces An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used ... 03/09/06 - 20060053267 - Scaling address space utilization in a multi-threaded, multi-processor computer Scaling address space utilization in a multi-threaded, multi-processor computer, including attaching to process memory of an exporting process a region of virtual memory specified in a cross-memory descriptor; requesting, by an importing thread of an importing process having process memory, a lightweight attachment of the region of virtual memory to ... 02/23/06 - 20060041735 - Pretranslating input/output buffers in environments with multiple page sizes Pretranslating input/output buffers in environments with multiple page sizes that include determining a pretranslation page size for an input/output buffer under an operating system that supports more than one memory page size, identifying pretranslation page frame numbers for the buffer in dependence upon the pretranslation page size, pretranslating the pretranslation ... 02/23/06 - 20060041734 - Associating mac addresses with addresses in a look-up table An ethernet switch associates addresses in a look-up table with received MAC addresses using a CRC algorithm, so that correspondence data about each MAC address can be stored in the corresponding section of the look-up table. When, as the look-up table is constructed, a given MAC address A0 hashes to ... 02/16/06 - 20060036831 - Multiprocessor A parallel computation apparatus as a multiprocessor includes functional modules as a plurality of processors having an optical communication function and capable of mutually cooperating, and an optical transmission line interconnecting the plurality of processors. Among the plurality of functional modules, the first functional module having a first information processing ... 12/08/05 - 20050273573 - System and method for gui supported specifications for automating form field extraction with database mapping A GUI (Graphical User Interface) supported specification method for form field extraction and database mapping in a computer system that includes converting a form file into a fixed electronic document format by using a GUI which is used to specify the form file and conversion parameters and extracting fields from ... 11/10/05 - 20050251643 - Memory arrangement A memory arrangement and method for operating the memory arrangement comprising a nonvolatile memory and at least one address translation unit, the nonvolatile memory having memory pages and at least one additional memory page, the memory pages and the additional memory page having physical addresses and the address translation unit ... 09/29/05 - 20050216696 - Multi-processor system and memory accessing method A multiprocessor system includes a plurality of microprocessors configured to operate on a plurality of operating systems, respectively, and a memory section configured to have a plurality of memory spaces respectively allocated to the plurality of microprocessors. Each of the plurality of microprocessors may include a translation look-aside buffer (TLB) ... 08/25/05 - 20050188176 - Apparatus and method for providing pre-translated segments for page translations in segmented operating systems A mechanism for generating pre-translated segments for use in virtual to real address translation is provided in which segments that are determined to meet a density threshold are promoted to a pre-translated segment class. The pages of these segments are moved to a contiguous portion of memory and the segment ... 08/25/05 - 20050188175 - Apparatus and method for lazy segment promotion for pre-translated segments A mechanism for generating pre-translated segments for use in virtual to real address translation is provided in which segments that are determined to meet a density threshold are promoted to a pre-translated segment class. The pages of these segments are moved to a contiguous portion of memory and the segment ... 08/18/05 - 20050182912 - Method of effective to real address translation for a multi-threaded microprocessor The present invention provides a method and apparatus for efficiently translating an effective address (EA) to a real address (RA) in an Effective to Real Address Translation (ERAT) table, in a main processing unit (MPU) having two or more threads. A thread, using an EA, presents the EA for lookup ... 08/11/05 - 20050177701 - Address coversion technique in a context switching environment According to some embodiments, a memory management unit receives a virtual address and provides a corresponding physical address. The memory management unit stores generated virtual address-to-physical address translations. If a virtual address-to-physical address translation is available for a particular virtual address, the memory management unit retrieves the corresponding physical address. ... 08/04/05 - 20050172098 - Immediate virtual memory Various embodiments of the present invention provide for immediate allocation of virtual memory on behalf of processes running within a computer system. One or more bit flags within each translation indicate whether or not a corresponding virtual memory page is immediate. READ access to immediate virtual memory is satisfied by ... 07/14/05 - 20050154855 - Method and apparatus for performing address translation in a computer system An address translation unit is provided for use in a computer system. The unit contains a set of page table entries for mapping from a virtual address to a packet address. Each page table entry corresponds to one page of virtual memory, and typically includes one or more specifiers. Each ... 06/30/05 - 20050144422 - Virtual to physical address translation A virtual to physical address translator in which a requesting process supplements a virtual memory address with a shortcut to a physical address associated with one level of a multi-level virtual address translation table. A second process, such as an I/O process, receives the shortcut and the virtual address and ... ### FreshPatents.com Support |