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Electrical Computers And Digital Processing Systems: Memory > Address Formation > Address Mapping (e.g., Conversion, Translation) > Virtual Addressing > Predicting, Look-ahead > Directories And Tables (e.g., Dlat, Tlb) Directories And Tables (e.g., Dlat, Tlb)Directories And Tables (e.g., Dlat, Tlb) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/12/06 - 20060230252 - System and method of improving task switching and page translation performance utilizing a multilevel translation lookaside buffer A system and method of improved task switching in a data processing system. First, a first-level cache memory casts out an invalidated page table entry and an associated first page directory base address to a second-level cache memory. Then, the second-level cache memory determines if a task switch has occurred. ... 09/21/06 - 20060212675 - Method and system for optimizing translation lookaside buffer entries A system for optimizing translation lookaside buffer entries is provided. The system includes a translation lookaside buffer configured to store a number of entries, each entry having a size attribute, each entry referencing a corresponding page, and control logic configured to modify the size attribute of an existing entry in ... 09/14/06 - 20060206686 - Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for ... 09/07/06 - 20060200644 - Storage medium for storing processing mode specifying information conversion program and processing mode specifying information conversion method The present invention provides a processing mode specifying information conversion method. The method includes: acquiring first information for specifying a processing mode of a first process in a first program by acquiring means, converting the acquired first information into second information for specifying a processing mode of a second process ... 08/31/06 - 20060195677 - Bank conflict avoidance in a multi-banked cache system A cache system comprises a plurality of cache banks, a translation look-aside buffer (TLB), and a scheduler. The TLB is used to translate a virtual address (VA) to a physical address (PA). The scheduler, before the VA has been completely translated to the PA, uses a subset of the VA's ... 07/20/06 - 20060161760 - Multiple contexts for efficient use of translation lookaside buffer The present invention provides a method and apparatus for increased efficiency for translation lookaside buffers by collapsing redundant translation table entries into a single translation table entry (TTE). In the present invention, each thread of a multithreaded processor is provided with multiple context registers. Each of these context registers is ... 05/25/06 - 20060112256 - Method and apparatus for address mapping A method and apparatus for address mapping are provided, wherein the method sets a first address region that is accessible by a processor when a system is booted and a second address region that is expanded by a virtual address, respectively. The first and second address regions are then mapped ... 05/11/06 - 20060101227 - Method and apparatus for sharing tlb entries A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses, for example into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may access address spaces in common. The mechanism further supports private TLB entries among ... ### FreshPatents.com Support |