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Electrical Computers And Digital Processing Systems: Memory > Address Formation > Address Mapping (e.g., Conversion, Translation) Address Mapping (e.g., Conversion, Translation)Address Mapping (e.g., Conversion, Translation) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/12/06 - 20060230251 - System and method for providing compact mapping between dissimilar memory systems A memory mapping system for providing compact mapping between dissimilar memory systems and methods for manufacturing and using same. The memory mapping system can compactly map contents from one or more first memory systems into a second memory system without a loss of memory space in the second memory system. ... 10/05/06 - 20060224858 - Sequencer address management Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the ... 10/05/06 - 20060224857 - Locking entries into translation lookaside buffers Two translation lookaside buffers may be provided for simpler operation in some embodiments. A hardware managed lookaside buffer may handle traditional operations. A software managed lookaside buffer may be particularly involved in locking particular translations. As a result, the software's job is made simpler since it has a relatively simpler, ... 09/21/06 - 20060212674 - Run level address mapping table and related method of construction A run level address mapping table and related method of construction is disclosed. The address mapping table is constructed on a run basis, e.g., a group of consecutive pages having consecutive logical or physical addresses. The run level address mapping table stores only an initial physical page number of each ... 09/14/06 - 20060206684 - Systems and methods for multi-frame control blocks Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control ... 08/31/06 - 20060195676 - Virtualization controller and data transfer control method Embodiments of the present invention are directed to systems and methods of controlling data transfer between a host system and a plurality of storage devices. One embodiment is directed to a virtualization controller for controlling data transfer between a host system and a plurality of storage devices. The virtualization controller ... 08/24/06 - 20060190699 - Method, medium, and apparatus transforming addresses of discs in a disc drive A method, medium, and apparatus transforming a logical address of a disc. The method includes mapping a plurality of physical addresses to a plurality of logical addresses with reference to the data transmission speeds of the heads so that a physical address for a head having a higher data transmission ... 08/10/06 - 20060179264 - Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 ... 08/03/06 - 20060174088 - Method and system for presenting contiguous element addresses for a partitioned media library According to one embodiment of the present invention, a controller that partitions a media library for multiple host applications can, for each partition, assign a base element address for an element type and associate physical element addresses for elements of an element type with an index value. For a partition, ... 07/27/06 - 20060168421 - Method of providing microcontroller cache memory A method of providing a deterministic microcontroller includes a providing a plurality of blocks of cache memories formed on the same integrated circuit as a microprocessor unit. ... 07/27/06 - 20060168420 - Microcontroller cache memory A deterministic microcontroller includes a plurality of blocks of cache memories formed on the same integrated circuit as the microprocessor unit. ... 07/20/06 - 20060161759 - Methods and apparatus for memory access within a computer system In a first aspect, a first method is provided for accessing a main memory. The first method includes the steps of (1) receiving a real address of the main memory that includes critical bits requiring conversion to bits of a physical address to start a memory access in a node ... 07/20/06 - 20060161758 - Multiple page size address translation incorporating page size prediction Page size prediction is used to predict a page size for a page of memory being accessed by a memory access instruction such that the predicted page size can be used to access an address translation data structure. By doing so, an address translation data structure may support multiple page ... 07/06/06 - 20060149918 - Memory with modifiable address map A memory device includes a flag register to modify the address map of the memory device based on the state of an input node on the memory device. ... 05/18/06 - 20060107019 - Flexible sub-column to sub-row mapping for sub-page activation in xdrtm drams A method, a computer program, and an apparatus are provided for flexible SC to SR mapping to enable sub-page activation in an XDR™ memory system. An XDR™ memory system may allow system page size to reduced by a factor of two (half-page activation) or four (quarter-page activation). In an XDR™ ... 05/11/06 - 20060101225 - Method and system for a multi-stream tunneled marker-based protocol data unit aligned protocol Aspects of a system for transporting information via a communications system may include a processor that enables establishing, from a local remote direct memory access (RDMA) enabled network interface card (RNIC), one or more communication channels, based on the transmission control protocol (TCP), between the local RNIC and at least ... 04/20/06 - 20060085623 - Data processing apparatus and method for flash memory A data processing apparatus and method are provided for a flash memory, wherein the data processing apparatus and method can easily determine whether data stored in the flash memory is valid. The data processing apparatus for a flash memory includes a user request unit which issues a request for performing ... 04/20/06 - 20060085622 - Method and system for managing address bits during buffered program operations in a memory device A method and system for managing a buffered program operation for plurality of words is described. In one aspect, the method and system include providing an internal buffer including a plurality of locations and at least one bit location for the plurality of locations. Each of the words is stored ... 04/20/06 - 20060085621 - Storage control apparatus and storage control method A storage control apparatus (20) is connected to a host apparatus (10) and to an external storage control apparatus (40) having an external storage device (42). The external storage control apparatus (40) stores address information representing at least either one of an external address which is an address of the ... 04/06/06 - 20060075207 - Information processing apparatus, process control method, and computer program An information processing apparatus includes a control operating system executing a process for allocating a plurality of logical processors to a physical processor in a time division manner, and a guest operating system for which a logical partition as an application entity of the logical processor is set. The control ... 04/06/06 - 20060075206 - Deterministic finite automata (dfa) instruction A computer-readable instruction is described for traversing deterministic finite automata (DFA) graphs to perform a pattern search in the in-coming packet data in real-time. The instruction includes one or more pre-defined fields. One of the fields includes a DFA graph identifier for identifying one of several previously-stored DFA graphs. Another ... 01/05/06 - 20060004983 - Method, system, and program for managing memory options for devices Provided are a method, system, and program for managing memory options for a device such as an I/O device. Private addresses provided by logic blocks within the device may be transparently routed to either an optional external memory or to system memory, depending upon which of the optional memories the ... 01/05/06 - 20060004982 - System and method for simulating real-mode memory access with access to extended memory In some embodiments, the invention involves a system and method relating to switching to protected mode to access extended memory while executing instruction code that is designed for real mode memory access. In at least one embodiment, the present invention is intended to enable complex option-ROM code to be executed ... 01/05/06 - 20060004981 - Apparatus and method for initialization of a double-sided dimm having at least one pair of mirrored pins A method and apparatus for initialization of a double-sided memory module having a least one pair of mirrored pins. In one embodiment, the method includes the generation of an opcode to initialize a first side of the memory module according to a first side pin routing. In one embodiment, the ... 12/29/05 - 20050289320 - Semiconductor device, microcomputer, and electronic equipment A semiconductor device comprising a bus master and a bus slave connected by a second bus is provided. A bus control unit (BCU) comprises a first relative address control circuit that performs a process for requesting the access using a relative address to a semiconductor storage medium through the second ... 12/01/05 - 20050268069 - Microcomputer with built-in electrically rewritable nonvolatile memory A microcomputer comprises a CPU; a nonvolatile memory; a plurality of volatile memories; a system bus; a program transfer bus; a program transfer section; an address conversion section; and a voltage detection section. The volatile memories include a plurality of memories switchable to be used as transfer and execution memories ... 12/01/05 - 20050268068 - Method and system for transferring data in a storage operation The invention provides a system and method for storing a copy of data stored in an information store. In one embodiment, a data agent reads one or more blocks containing the data from the information store. The data agent maps the one or more blocks to provide a mapping of ... 12/01/05 - 20050268067 - Method and apparatus for memory-mapped input/output A method of managing memory mapped input/output (I/O) for a run-time environment is disclosed, in which opaque references are used for accessing information blocks included in files used in a dynamic run-time environment. The information block is stored in a shared memory space of pages that are each aligned on ... 11/24/05 - 20050262327 - Data transfer control circuit, control apparatus and data transfer method A data transfer control circuit is connected between a first bus and a second bus. The first bus is connected with a first CPU and a first memory. The second bus is connected with a second CPU and a second memory. The data transfer control circuit includes a temporary memory ... 10/06/05 - 20050223188 - Addressing scheme supporting variable local addressing and variable global addressing A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first ... 10/06/05 - 20050223187 - Memory mapping control apparatus, information storage controller, data moving method, and data moving program PC 20 as an example of memory mapping control apparatus is comprised of a receiver 21 for receiving source data in an as-stored format in a memory 11 of a source mobile station A, and information (version information, data structure information, etc.) for specifying data structures of mobile station A ... 10/06/05 - 20050223186 - Device-level address translation within a programmable non-volatile memory device A programmable non-volatile memory device includes block switching logic that enables device-level translation rules to be changed. The device-level translation rules map the external addresses received by the flash memory device to the internal addresses of the programmable non-volatile memory device. Because the device-level translation rules are changeable, the physical ... 09/08/05 - 20050198463 - Data managing method for memory apparatus A block correlation table includes block addresses of unusable block portions in an irreversibly writeable memory and includes addresses of associated substitute block portions in the irreversibly writeable memory. A request for data stored at a logical address is received from a host processor. A physical address in the irreversibly ... 08/11/05 - 20050177700 - System for providing multiple window environments in a mobile computing system and method thereof Disclosed is a system for providing multiple window environments in a mobile computing system and a method thereof, which enables a user to conveniently and selectively use a window system suitable for the use environment. A plurality of sub-window systems having different user interfaces and application programs are installed in ... 06/09/05 - 20050125627 - Methods and apparatus for caching a location index in a data storage system One embodiment is a system for locating content on a storage system, in which the storage system provides a location hint to the host of where the data is physically stored, which the host can resubmit with future access requests. In another embodiment, an index that maps content addresses to ... 06/09/05 - 20050125626 - Methods and apparatus for facilitating access to content in a data storage system One embodiment is a system for locating content on a storage system, in which the storage system provides a location hint to the host of where the data is physically stored, which the host can resubmit with future access requests. In another embodiment, an index that maps content addresses to ... 06/09/05 - 20050125625 - Methods and apparatus for parsing a content address to facilitate selection of a physical storage location in a data storage system One embodiment is a system for locating content on a storage system, in which the storage system provides a location hint to the host of where the data is physically stored, which the host can resubmit with future access requests. In another embodiment, an index that maps content addresses to ... ### FreshPatents.com Support |