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Electrical Computers And Digital Processing Systems: Memory > Storage Accessing And Control > Access Timing Access TimingAccess Timing patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236057 - Memory access method with delayed write control signal and data processing apparatus The invention provides a data processing apparatus having a data input unit (108) for inputting data, at least one processor unit (107) for carrying out data processing steps (201, 201a, 201b) for the input data, at least one memory unit (402) for storing processed data, the data being able to ... 10/05/06 - 20060224848 - Method and apparatus for reducing system inactivity during time data float delay and external memory write The invention comprises a system for reducing inactive periods in an integrated circuit. The integrated circuit is coupled to an external peripheral by an external data bus. The integrated circuit has a processor coupled to an internal data bus. The system comprises the following. An external bus circuit is coupled ... 10/05/06 - 20060224847 - Memory interface architecture for maximizing access timing margin An apparatus comprising a control circuit, a buffer circuit and a memory. The control circuit may be configured to present a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a ... 09/14/06 - 20060206679 - System and method for read synchronization of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and ... 09/07/06 - 20060200642 - System and method for an asynchronous data buffer having buffer write and read pointers A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between ... 08/17/06 - 20060184757 - Data memory controller that supports data bus invert The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces ... 08/17/06 - 20060184756 - Semiconductor memory module for improvement of signal integrity A semiconductor memory module has a module board on both sides of which semiconductor memory components are arranged and on an upper face of which a control component is arranged. The control component is connected to the semiconductor memory components via a module bus and bus spurs. The bus is ... 08/17/06 - 20060184755 - Semiconductor memory device and memory system using same There is provided a semiconductor memory device and a memory system using the same. The semiconductor memory device includes an input data delay time adjustor for varying an input delay time, selecting one bit of a n-bit input data, delaying the selected one bit by the input delay time and ... 08/17/06 - 20060184754 - Method and apparatus to avoid collisions between row activate and column read or column write commands A method and apparatus to avoid collisions between row activate and column read or column write commands is presented. A memory controller includes control logic, activate allowed logic, and last column counter logic. The control logic sends particular values to the activate allowed logic and the last column counter logic ... 07/27/06 - 20060168417 - Random access memory having low initial latency A random access memory comprises an array of memory cells and a controller. The controller is configured to access the array of memory cells in a double data rate prefetch mode in response to a read command and in a single data rate mode after the first double data rate ... 07/27/06 - 20060168416 - Data processing circuit with multiplexed memory A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for ... 07/13/06 - 20060155948 - Semiconductor memory system and method for data transmission A semiconductor memory system is proposed, in which the transmission of memory data of a burst that follows command/address data of a write/read command is identified by means of a modified clock signal. The modified clock signal has identifying regions with masked-out clock edges, so that the transmission of memory ... 06/22/06 - 20060136692 - Detection circuit for mixed asynchronous and synchronous memory operation A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the ... 06/15/06 - 20060129776 - Method, system and memory controller utilizing adjustable read data delay settings A method, system and memory controller that uses adjustable read data delay settings. The memory controller includes control transmit circuitry, data reception circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data reception circuitry receives data signals ... 05/25/06 - 20060112250 - Dynamic control of memory access speed A memory system is disclosed in which the access speed may be adjusted. The memory system may include memory and a memory controller. The memory controller may be configured to generate a plurality of control signals to access the memory, and adjust the timing between the control signals to change ... 05/25/06 - 20060112249 - Apparatus and method to set the signaling rate of a switch domain disposed within an information storage and retrieval system A method is disclosed to set the signaling rate of a switch domain disposed in an information storage and retrieval system. The method establishes a switch domain target operating speed, and determines if that switch domain target operating speed comprises a first signaling rate. If the switch domain target operating ... 05/18/06 - 20060107011 - Method and apparatus for self-adjusting input delay in ddr-based memory systems A method and apparatus are provided for interfacing with a synchronous dynamic memory in which memory commands are provided to the memory. The memory is accessed in response to the memory commands. Read data is captured in a data capture circuit having a delay setting. The delay setting is updated ... 05/11/06 - 20060101218 - Memory controller-adaptive 1t/2t timing control Circuits, methods, and apparatus that adaptively control 1T and 2T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as an additional memory interface, each having a number of address and control lines. The address and control lines of the ... 05/04/06 - 20060095701 - System, method and storage medium for a memory subsystem with positional read data latency A memory subsystem with positional read data latency that includes a cascaded interconnect system with one or more memory modules, a memory controller and one or more memory busses. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected by ... 04/27/06 - 20060090054 - System controlling interface timing in memory module and related method A memory system for controlling interface timing in a memory module and a related timing control method are disclosed. The memory system comprises a memory module having a memory module controller configured to control interface timing of a plurality of memory devices in accordance with memory information and memory signal ... 04/20/06 - 20060085616 - Method and system for dynamically adjusting dram refresh rate One embodiment is a method of dynamically adjusting a rate at which a dynamic random access memory (“DRAM”) module is refreshed in a computer system. The method comprises monitoring a plurality of system conditions; detecting a change in at least one of the monitored system conditions; responsive to the detection, ... 03/30/06 - 20060069895 - Method, system and memory controller utilizing adjustable write data delay settings A method, system and memory controller that uses adjustable write data delay settings. The memory controller includes control transmit circuitry, data transmit circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data transmit circuitry transmits data signals ... 03/30/06 - 20060069894 - De-coupled memory access system and method A de-coupled memory access system including a memory access control circuit configured to generate first and second independent, de-coupled time references. The memory access control circuit includes a read initiate circuit responsive to the first time reference and a read signal for generating a read enable signal, and a write ... 03/30/06 - 20060069893 - Host implementation of triangular asynchronous replication Storing recovery data includes a host processor writing data to a local storage device, the host processor causing the local storage device to accumulate chunks of data corresponding to writes by the host processor, where each chunk of data represents data written before a first time and after a second ... 02/23/06 - 20060041730 - Memory command delay balancing in a daisy-chained memory topology A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay ... 02/16/06 - 20060036828 - Memory device sequencer and method supporting multiple memory device clock speeds A sequence state matrix has a plurality of time slots for storing a plurality of memory device signals. The memory device signals are loaded into the matrix by a sequencer load unit, which loads the memory device signals at locations in the matrix corresponding to the times that the signals ... 02/16/06 - 20060036827 - System, method and storage medium for providing segment level sparing A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus. ... 02/16/06 - 20060036826 - System, method and storage medium for providing a bus speed multiplier A memory subsystem for providing a bus speed multiplier. The memory subsystem includes one or more memory modules operating at a memory module data rate. The memory subsystem also includes a memory controller and one or more memory busses. The memory busses operate at four times the memory module data ... 02/02/06 - 20060026375 - Memory controller transaction scheduling algorithm using variable and uniform latency A memory method may select a latency mode, such as read latency mode, based on measuring memory channel utilization. Memory channel utilization, for example, may include measurements in a memory controller queue structure. Other embodiments are described and claimed. ... 01/05/06 - 20060004976 - Shared memory architecture A wireless communications architecture having first and second synchronous memory devices coupled to a virtual channel memory controller by corresponding first and second data buses, and a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices. The first and second ... 12/29/05 - 20050289313 - Synchronous flash memory with status burst output A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The ... 12/29/05 - 20050289312 - Methods, apparatus and computer programs for scheduling storage requests Provided are methods, apparatus and computer programs for scheduling storage input and/or output (I/O) requests. A method for scheduling storage access requests determines a request processing sequence calculated to maximize SLA-based revenues achievable from processing a number of requests. A storage controller includes a scheduler which implements a revenue-based scheduling ... 12/22/05 - 20050283582 - Smart memory read out for power saving A method and a circuit are given, to implement and realize power saving Sense Electronics Endowed (SEE) memory using modified memory read cycles, named as Smart Memory Readout (SMR). In an SMR-mode read cycle, the memory is only active a small fraction of a clock cycle thus saving power. In ... 12/22/05 - 20050283581 - Data reading structure A data reading structure for a 8-bit microprocessor to read several bytes of data at a time has a memory module and a selector module. The memory module has a first memory having a first and second data output ports and a second memory has a third and fourth data ... 12/08/05 - 20050273566 - Memory access control apparatus and memory access control method A memory controller determines a load level based on the number of connected memory devices informed by a switch or the like. If it is determined that the load level is high, the memory controller increases the number of cycles for issuing command/address signals, and if it is determined that ... 12/01/05 - 20050268062 - Hierarchical storage apparatus and control apparatus thereof A method for managing data stored in a hierarchical storage unit of a storage apparatus is disclosed. The storage unit includes a first storage medium having a first access speed and a second storage medium having a second access speed. The first access speed is different from the second access ... 12/01/05 - 20050268061 - Memory channel with frame misalignment Memory apparatus and methods align frames so that portions of more than one frame may be received at a memory agent during a cycle of a base clock for a memory device. One of the frames may be a command frame having a memory device command portion. The memory device ... 12/01/05 - 20050268060 - Method and system for terminating write commands in a hub-based memory system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is directed to the hub to develop memory access ... 12/01/05 - 20050268059 - On-die termination snooping for 2t applications in a dynamic random access memory device A method and apparatus for controlling the on-die termination of a memory system. The method comprises snooping a command bus in response to a first plurality of command signals clocked at 1T and enabling the on-die termination in response to a second plurality of command signals clocked at 2T and ... 11/24/05 - 20050262323 - System and method for improving performance in computer memory systems supporting multiple memory access latencies A memory system having multiple memory devices reduces average access latency by enabling different latencies for different regions of physical memory, providing an address map conducive to placing frequently accessed memory addresses into the lowest latency regions of physical memory; and assigning the frequently accessed memory addresses to the lowest ... 11/10/05 - 20050251638 - Devices, systems and methods for conditional instructions A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction ... 10/27/05 - 20050240745 - High speed memory control and i/o processor system An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive ... 10/27/05 - 20050240744 - Data mask as write-training feedback flag Methods and apparatuses that enable memory devices to inform graphical processing systems about the results of WRITE de-skew training. A WRITE-TRAINING mode is added to a memory device. When the WRITE-TRAINING mode is asserted the memory data mask (DM) pin is converted to an output port. Incoming WRITE data is ... 10/27/05 - 20050240743 - Method and apparatus for accessing data storage systems Improved techniques for accessing data storage systems are disclosed. These techniques detect, correct and prevent undesirable access delays experienced in storage systems. “Slow-access” refers to an access operation that does not successfully complete within a predetermined amount of time. When slow-access is detected, an attempt is made to provide data ... 10/27/05 - 20050240742 - Method and apparatus for improving performance of data storage systems Techniques for improving access time in data storage systems are disclosed. These techniques can be used to prevent undesirable access delays that are often experienced in conventional storage systems. “Slow-access” can be defined as an access operation that does not successfully complete within a predetermined amount of time. The “slow-access” ... 09/29/05 - 20050216690 - Data transfer control method, and peripheral circuit, data processor and data processing system for the method A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to ... 09/22/05 - 20050210215 - Semiconductor device permitting rapid data reading and writing between processor and memory In a read operation, a memory circuit successively performs precharge, sense operation and data output operation, each in 0.5 cycle of a clock signal. A write detection circuit, in response to switching from a write operation to a read operation, sends a signal to the memory circuit to make it ... 09/15/05 - 20050204112 - Method and system to order memory operations Briefly, in accordance with an embodiment of the invention, a system and method to order memory operations is provided. The method may include using at least one signal to indicate that a particular kind of memory operation is not globally observable but is observable by at least one processor of ... 09/15/05 - 20050204111 - Command scheduling for dual-data-rate two (ddr2) memory devices Embodiments of the present invention include an integrated circuit that has eight queues to receive commands for a memory device, the memory device having four banks, the eight configurable queues having a first queue and a second queue to map to a first bank. The integrated circuit also includes logic ... 09/08/05 - 20050198459 - Apparatus and method for open loop buffer allocation A method and apparatus for open loop buffer allocation. In one embodiment, the method includes loading requested data within a buffer according to a load rate. Concurrent with the loading of data within the buffer, the data is forwarded from the buffer according to drain rate. In situations where the ... 08/11/05 - 20050177695 - Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data ... 08/04/05 - 20050172095 - Dual edge command in dram A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on ... 07/28/05 - 20050166026 - Configurable width buffered module having switch elements A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device with at least one switch element. A buffer device, such as a configurable width buffer device, is positioned between or with at least one integrated circuit memory device positioned on a substrate ... 07/21/05 - 20050160247 - Transceiver with latency alignment circuitry A transceiver device comprises a transmitter to transmit signals over a plurality of conductors to a memory device. An interface receives control information from a serial communication path coupled to a controller device. The control information is provided to the memory device as the signals using the transmitter. A register ... 07/21/05 - 20050160246 - Method and device for controlling a memory access The invention relates to a method and a corresponding device for controlling a memory access, wherein a number of waiting states is established for the memory access to a storage device (FLASH/ROM, RAM, IO module) for a central control unit (CPU). A memory access is made possible in that the ... 07/21/05 - 20050160245 - Novel fifo memory architecture and method for the management of the same A FIFO memory with a frequency f and a size of M n-bit words, to successively store n-bit words received serially at an input and give said words serially at an output in the order in which they are stored, comprises a basic memory with a frequency f/2, capable of ... 07/07/05 - 20050149685 - Transceiver with latency alignment circuitry A transceiver comprises a first interface to receive a first signal, through a first channel, from a memory device. A transmitter transmits a second signal that represents the first signal, through a second channel, to a master device. A plurality of registers stores a plurality of values provided by the ... 06/30/05 - 20050144409 - Data processing device and method utilizing latency difference between memory blocks Each of a plurality of memory blocks returns data in different latency in reply to a data request from a request source. The closer a request destination memory block is to the request source, in the shorter latency the data is returned. ... 06/16/05 - 20050132159 - Memory hub bypass circuit and method A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurality of memory devices. ... 06/16/05 - 20050132158 - Memory device signaling system and method with independent timing calibration for parallel signal paths A memory system includes a memory controller and a memory component coupled to each other. The memory controller includes an interface to receive a first signal and a second signal from the memory component, wherein the first signal comprises a first symbol and the second signal comprises a second symbol. ... 06/09/05 - 20050125620 - Methods and apparatus for balancing memory access latency and bandwidth A method and apparatus for balancing memory access latency and bandwidth is generally described. In accordance with one example embodiment of the invention, a method comprising determining at least one characteristic of a memory request, and selectively leaving an accessed memory page open after a memory access based, at least ... ### FreshPatents.com Support |