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Electrical Computers And Digital Processing Systems: Memory > Storage Accessing And Control > Control Technique > Prioritizing PrioritizingPrioritizing patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.08/03/06 - 20060174073 - Priority initialization system A computer storage system includes a supervisor algorithm to detect a host computer's initiator logging in. The supervisor algorithm identifies data storage devices associated with the newly logged-on initiator and tags logical unit number control blocks (“LUNCBs”) as having priority in an initiation process. The supervisor algorithm assigns a task ... 06/08/06 - 20060123206 - Prioritization of out-of-order data transfers on shared data bus Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that ... 04/27/06 - 20060090046 - Banking render cache for multiple access A cache memory system may be is organized as a set of numbered banks. If two clients need to access the cache, a contention situation may be resolved by a contention resolution process. The contention resolution process may be based on relative priorities of the clients. ... 03/16/06 - 20060059320 - Memory control device It is an object of the present invention to provide a memory controller which prevents successive access to the same bank of SDRAM and improves processing time. A memory controller (105) of the present invention is a memory controller for controlling memory which has a plurality of banks and can ... 02/16/06 - 20060036820 - Data storage system There are connected a plurality of hosts 1 to L, a plurality of targets 1 to M and a plurality of initiators 1 to N, through a network. Each target has a managing unit which decides by itself the target search information broadcast from the initiator onto the network. In ... 02/02/06 - 20060026371 - Method and apparatus for implementing memory order models with order vectors In one embodiment of the present invention, a method includes generating a first order vector corresponding to a first entry in an operation order queue that corresponds to a first memory operation, and preventing a subsequent memory operation from completing until the first memory operation completes. In such a method, ... 12/29/05 - 20050289306 - Memory read requests passing memory writes Memory read and write requests are received. The read is received in accordance with a communication protocol that has a transaction ordering rule in which a memory read cannot pass a memory write. The memory read and write requests are forwarded to the first device in accordance with another communication ... 12/29/05 - 20050289305 - Queue structure with validity vector and order array According to some embodiments, a queue structure includes a validity vector and an order array. ... 12/08/05 - 20050273564 - Memory controller A memory controller module that includes a memory interface and at least two memory controllers, each memory controller to control a category of memory devices. A circuitry enables the at least two memory controllers to control access to memory devices based on information indicating the category or categories of the ... 12/01/05 - 20050268051 - Prioritized bus request scheduling mechanism for processing devices A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a ... 10/20/05 - 20050235119 - Methods and mechanisms for proactive memory management A proactive, resilient and self-tuning memory management system and method that result in actual and perceived performance improvements in memory management, by loading and maintaining data that is likely to be needed into memory, before the data is actually needed. The system includes mechanisms directed towards historical memory usage monitoring, ... 06/23/05 - 20050138304 - Performing memory ras operations over a point-to-point interconnect In some embodiments, a memory transaction is received that was sent over an unordered interconnect. A determination is made as to whether an address conflict exists between the memory transaction and another memory transaction. If the address conflict exists the memory transaction is forwarded only after waiting until the conflict ... 06/16/05 - 20050132153 - Method and apparatus of arranging priority queue and arbitrating for memory access requests A method and an apparatus of memory access request priority queue arbitration comprises sorting the requests into plurality of different priority levels firstly. The priority queues of different priority levels are arranged respectively according to the following steps: counting the cycles and latencies of each access request; counting the total ... ### FreshPatents.com Support |