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Electrical Computers And Digital Processing Systems: Memory > Storage Accessing And Control > Control Technique > Interleaving InterleavingInterleaving patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236045 - Apparatus for deinterleaving interleaved data using direct memory access Deinterleaving is performed using a “smart” direct memory access (DMA) function. The deinterleaver, which may be a modified DMA controller, can be programmed with a step size so that the deinterleaver reads every Nth byte from the memory. The deinterleaver automatically increments the source memory address by the step size ... 07/27/06 - 20060168408 - System and method for interleaving sdram device access requests A method and system is provided for interleaving multiple cycles streams from clients seeking SDRAM access. More particularly, a master scoreboard register is established for enabling the interleaving of many clients SDRAM access requests into a single stream optimized for maximum packing density of the different streams, thereby reducing the ... 05/04/06 - 20060095694 - Method of memory space configuration A method is disclosed for utilizing at least one bit within the logical address code of a memory unit formed by Dynamic Random Access Memory (DRAM) to be the control code for interleaving the memory space to different memory ranks. First, the distributive rule of the data is defined. Next, ... 03/23/06 - 20060064557 - Interleaving data blocks A method for interleaving includes presenting a physical storage device as a plurality of logical storage devices each having a unique address. Streams of data blocks are received via each address. The data blocks are interleaved. Instructions are routed to write the interleaved data blocks to the storage device in ... 02/16/06 - 20060036819 - Interleaver for iterative decoder Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implemented within communication devices that implement two distinct SISOs that operate cooperatively ... 12/15/05 - 20050278491 - Memory interleaving A central processor unit (CPU) accesses memory to read and write data and to read and execute program instructions. A problem arises when accessing slower Flash or electrically programmable read only memory (EPROM) with a faster CPU. A method and system has been devised which uses interleaving techniques and memory ... 11/03/05 - 20050246508 - System and method for interleaving memory One system may comprise an interleave system that determines a desired interleave for at least a selected portion of a distributed memory system. A migration system is associated with the interleave system to migrate blocks of data to implement the desired interleave. ... 08/04/05 - 20050172091 - Method and an apparatus for interleaving read data return in a packetized interconnect to memory A method and an apparatus to process read data return has been disclosed. In one embodiment, the method includes packing a cache line of each of a number of read data returns into one or more packets, splitting each of the one or more packets into a plurality of flits, ... ### FreshPatents.com Support |