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Electrical Computers And Digital Processing Systems: Memory > Storage Accessing And Control > Control Technique Control TechniqueControl Technique patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236043 - Memory controller A memory system includes a memory and a plurality of memory controllers for accessing the memory. One of the plurality of memory controllers synchronizes the one of the plurality of memory controllers with the plurality of memory controllers. ... 10/19/06 - 20060236042 - Training sequence for deswizzling signals Data is transmitted from a memory device along with a training sequence to deswizzle the data. The training sequence may be sent, for example, when the memory device is initialized, or it may be appended to the data. A memory controller may include logic to receive the data and training ... 10/12/06 - 20060230242 - Memory for multi-threaded applications on architectures with multiple locality domains Embodiments of the invention relate to multi-threaded and multi-locality-domain applications. In an embodiment, memory in the form of linked lists for each locality domain is allocated in which a linked list of buffers from the same locality domain is created for that locality domain. When a thread requests memory, e.g., ... 10/12/06 - 20060230241 - Buffer architecture for data organization An embodiment includes an apparatus that includes a first data processor component to output data in a first data organization. The apparatus also includes a data storage logic to receive the data output from the first data processor component. The data storage logic is to rearrange the data into a ... 10/05/06 - 20060224841 - Information processing device and information processing method An information processing device is provided in which a valid initial program is transferred to a RAM while avoiding a invalid block which is present in a low reliable storage device, such as a NAND-type flash memory or the like. A management information storing section 29 stores management information 30 ... 09/28/06 - 20060218361 - Electronic storage device with rapid data availability An electronic storage device provides rapid data availability. The rapid data availability relates to sequences of reads and writes performed by the ESD responsive to critical events, such as power-up sequences or sequences of read and/or write operations. A sequence of reads is performed upon detecting a critical event. A ... 09/28/06 - 20060218360 - Method, apparatus and program storage device for providing an optimized read methodology for synchronously mirrored virtual disk pairs A method, apparatus and program storage device for providing an optimized read methodology for synchronously mirrored virtual disk pairs are disclosed. A VDisk to use for read operations is determined based on loading of synchronously mirrored VDisk pairs. Based on the loading, the determined request is used to satisfy the ... 09/28/06 - 20060218359 - Method and system for managing multi-plane memory devices A computational system comprising a controller and a multi-plane solid state memory device accessible to the controller is disclosed. The controller is configured to provide access to a virtual block having a virtual block address that represents a first block from a first plane of the multi-plane solid state memory ... 09/21/06 - 20060212666 - Memory hub and method for providing memory sequencing hints A memory module includes a memory hub coupled to several memory devices. The memory hub is also coupled to receive a memory packet from a system controller containing a memory hint indicative of the subsequent operation of the memory devices. The memory module uses the hint to adjust the operation ... 09/21/06 - 20060212665 - System and method for online firmware update and on-screen-display parameters modification An online firmware update system and its control interface. The control interface couples to microprocessor, built-in storage unit, and rewritable memory. The control interface includes multiplexer, control register, and bus interface unit. The multiplexer includes selection terminal, output terminal, and control signal input terminal. When the control signal enables the ... 09/14/06 - 20060206674 - Optical disc drive and program code updating method thereof An optical disc drive is disclosed. The optical disc drive includes a non-volatile memory storing a first program code; a memory providing a space needed when executing the first program code; and a control module determining whether to update the first program code stored in the non-volatile memory or not. ... 09/14/06 - 20060206673 - Method for controlling access of dynamic random access memory module A method for controlling access for a DRAM module applicable to a substrate provided with at least a DRAM module slot of either a first or second specification, a memory controller and a BIOS program is proposed. Thus, access control for first and second DRAM modules installed in the DRAM ... 08/31/06 - 20060195665 - Access control device, method for changing memory addresses, and memory system A memory control device detects memory accesses and communicates with a plurality of memory modules that are serially connected. The memory control device changes the allocation of addresses for the plurality of memory modules in accordance with the detection of memory accesses in the detection step. ... 08/31/06 - 20060195664 - Terminal for use in a system interfacing with storage media A method is adopted in a control apparatus for controlling ID information stored in a storage medium in conjunction with a terminal for reading the ID information from the storage medium and used to catalog information for the storage medium into a memory employed in the control apparatus. In an ... 08/24/06 - 20060190691 - Die-to-die interconnect interface and protocol for stacked semiconductor dies A system and method for a die-to-die interconnect interface and protocol for stacked semiconductor dies. One preferred embodiment comprises an integrated circuit (IC) package comprising a first semiconductor die that includes an interface to a memory-mapped device, a second semiconductor die that does not include an interface to a memory ... 08/17/06 - 20060184753 - Full access to memory interfaces via remote request A system and method for enabling a processor to access a memory not directly coupled to the processor. A memory request, including a request identifier field, is issued by a processor to a local memory management unit (MMU). Using the request identifier field, the local MMU determines whether the memory ... 08/17/06 - 20060184752 - Memory controller and memory control system predicting non-contiguous access A memory controller for controlling operation of a memory accessed by a processor, includes an access information storage circuit storing history information of non-contiguous access of non-contiguous addresses of data accessed by the processor, a prediction circuit predicting a non-contiguous access based on the history information of non-contiguous access, an ... 08/10/06 - 20060179260 - Semiconductor memory device and a data write and read method thereof Provided are a semiconductor memory device and a data write and read method thereof. The semiconductor memory device includes a write data controller, an address controller, and a read data controller. The write data controller writes data received with an address to a first memory cell corresponding to the address ... 08/10/06 - 20060179259 - Data processing apparatus and method for controlling access to memory A data processing apparatus and method are provided for controlling access to memory. The data processing apparatus comprises main processing logic operable to execute a sequence of instructions in order to perform a process, and subsidiary processing logic operable to perform at least part of the process on behalf of ... 08/03/06 - 20060174072 - Electronic control unit analysis A system for acquiring information on the operation of an electronic control unit (ECU) includes a controller and a non-volatile memory. The controller is coupled to address and data buses of a central processing unit (CPU), which is located within an electronic control unit (ECU). The controller includes a register ... 08/03/06 - 20060174071 - System and method for handling status commands directed to partitioned media library Embodiments of the present invention provide a method and system for handling status commands directed to a partitioned media library. A controller (e.g., storage router or other device) that controls access to the physical media library can receive a status command and determine whether it should respond to the status ... 07/27/06 - 20060168407 - Memory hub system and method having large virtual page size A memory system and method includes a memory hub controller coupled to a plurality of memory modules through a high-speed link. Each of the memory modules includes a memory hub coupled to a plurality of memory devices. The memory hub controller issues a command to open a page in a ... 07/20/06 - 20060161745 - Methods of operating memory systems including memory devices set to different operating modes and related systems A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality ... 07/20/06 - 20060161744 - Logic embedded memory having registers commonly used by macros A semiconductor integrated circuit device includes a plurality of memory macros, macro-common register block, and memory macro operation setting circuits. The macro-common register block has macro-common registers which are provided outside the plurality of memory macros and supply memory macro operation specifying signals to the plurality of memory macros. The ... 07/20/06 - 20060161743 - Intelligent memory array switching logic Techniques and circuitry that support switching operations required to exchange data between memory arrays and external data pads are provided. In a write path, such switching operations may include latching in and assembling a number of bits sequentially received over a single data pad, reordering those bits based on a ... 07/20/06 - 20060161742 - Communication system and method, information processing apparatus and method, information managing apparatus and method, recording medium, and program A communications system and method, an information processing apparatus and method, an information management apparatus and method, a recording medium and a program make it possible to efficiently and comfortably make use of contents, which are stored in one server, from a plurality of devices connected via a network. In ... 07/13/06 - 20060155942 - Storage control subsystem for managing logical volumes The present invention provides a storage control subsystem that facilitates logical volume access management by a host. Before copying, the host instructs a disk array device to identify the states of target logical volumes and collect information in control memory, whereupon the disk array device reads information in the control ... 07/13/06 - 20060155941 - Program rewriting system, boot loader, storage medium, and electronic control unit A system is communicably coupled to an external device at least when rewriting, at least in a module, a first application program stored in a first memory of the system into a second application program stored in the external device. In the system, a receiving unit is configured to receive ... 07/13/06 - 20060155940 - Multi-queue fifo memory systems that utilize read chip select and device identification codes to control one-at-a-time bus access between selected fifo memory chips Multi-Q FIFO memory systems include a plurality of multi-Q first-in first-out (FIFO) memory chips electrically coupled to a data output bus. The plurality of multi-Q FIFO memory chips, which are responsive to respective identification codes ID and respective read chip select signals (/RCS), are configured to support an enhanced multi-chip ... 07/06/06 - 20060149907 - System and method for using virtual memory for redirecting auxilliary memory operations A method for using virtual memory for redirecting auxiliary memory operations redirects the auxiliary memory write operations of a process to a buffer after capturing the state of the auxiliary memory at various times during the method in three buffers. After the write operations have ended, the auxiliary memory is ... 06/22/06 - 20060136684 - Method and system for accessing auxiliary data in power-efficient high-capacity scalable storage system A method for preparing data units for access in a data storage system is disclosed. The data storage system includes multiple storage devices having data units. All the storage devices of the data storage system are not powered on at the same time. The method includes preparing and storing the ... 06/22/06 - 20060136683 - Arbitration system and method for memory responses in a hub-based memory system A memory hub includes a local queue that stores local memory responses, a bypass path that passes downstream memory responses, and a buffered queue coupled to the bypass path that stores downstream memory responses from the bypass path. A multiplexer is coupled to the local queue, buffered queue, and the ... 06/22/06 - 20060136682 - Method and apparatus for arbitrarily initializing a portion of memory Techniques for initializing an arbitrary portion of memory with an arbitrary pattern includes using a memory controller for performing sequenced read and write operations. The memory controller receives address data, length data and pattern data on a data bus connected to a processor. The address data indicates a location in ... 06/22/06 - 20060136681 - Method and apparatus to support multiple memory banks with a memory block A memory controller system includes a memory command storage module to store commands for a plurality of memory banks. The system includes a plurality of control mechanisms, each of which includes first and second pointers, to provide, in combination with a next field in each module location, a link list ... 06/22/06 - 20060136680 - Capacity on demand using signaling bus control An apparatus and method is disclosed for providing capacity on demand using control to alter latency and/or bandwidth on a signaling bus in a computer system. If additional capacity is required, authorization is requested for additional capacity. If authorized, bandwidth of the signaling bus is increased to provide additional capacity ... 06/15/06 - 20060129767 - Method and memory controller for scalable multi-channel memory access An electrical device is connected to at least one memory accessing unit and to a memory including at least one physical memory module. The device includes at least one access channel circuit connected to the least one memory accessing unit via at least one system bus and to the at ... 06/08/06 - 20060123205 - Control data storage apparatus and process Control data storage apparatus includes a memory section including a plurality of control data memory blocks to store control data. There is further provided a control section to determine a selected memory block to store control data by selecting from the control data memory blocks. ... 06/01/06 - 20060117152 - Transparent four rank memory module for standard two rank sub-systems A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates ... 05/25/06 - 20060112241 - System, method and apparatus of securing an operating system Embodiments of the present invention provide a method, apparatus and system of securing an operating system. The apparatus, according to some demonstrative embodiments of the invention, may include a memory access controller to receive from a processor a program counter representing a requested address of a memory to be accessed ... 05/25/06 - 20060112240 - Priority scheme for executing commands in memories A command execution priority scheme for memories is disclosed. The priority scheme is directed to systems and techniques for storing and retrieving data from memory. A command queue may be used to receive a plurality of commands, each of the commands requesting access to the memory. A command selector may ... 05/25/06 - 20060112239 - Memory device for use in a memory module A memory device for use in a memory module and method for operating the memory device are provided. In one embodiment, the memory device comprises a memory array, a memory access logic for controlling access to the memory array depending on a command data, a command interface for establishing a ... 05/18/06 - 20060107002 - Method, system, and program for an adaptor to read and write to system memory Provided are a method, system, and program for an adaptor to read and write to system memory. A plurality of blocks of data to write to storage are received at an adaptor. The blocks of data are added to a buffer in the adaptor. A determination is made of pages ... 05/18/06 - 20060107001 - Arbitration scheme for memory command selectors An arbitration structure, a method, and a computer program are provided for an arbitration scheme that can handle a plurality of memory commands in an operating system. Typically, in a memory system there are three types of memory commands: periodic, read, and write. An arbitration scheme determines the order of ... 05/11/06 - 20060101211 - Apparatus, system, and method for generating a name for a system of devices An apparatus, system, and method are disclosed for generating a name for a system of devices. An identifier identifies each component in the system. Once each component is identified, information such as the World Wide Name (WWN) of each component is stored in a database. Additional information such as the ... 05/11/06 - 20060101210 - Register-based memory command architecture A device and method for interfacing a processor to a non-volatile memory that may use a command based architecture to receive data from the processor and a long latency architecture that includes a microcode engine within the memory to control simple read, erase and program operations and further capable of ... 05/04/06 - 20060095693 - Method for communicating between host and storage device, storage device, host, and system comprising storage device and host Embodiments of the invention improve the efficiency of communication processing between a host and a storage device. In one embodiment, a data processing system includes a storage device and a host. The host gives the storage device an instruction to perform specified processing, and an instruction as to whether or ... 05/04/06 - 20060095692 - Programmable control interface device A programmable control interface is for circuits using complex commands. The programmable interface includes a memory for storing sampled commands and a sequencing circuit. The sequencing circuit is programmable. Thus, a processor downloads into the programmable interface a sequencing specific to the sequence of commands. Once the programmable interface has ... 05/04/06 - 20060095691 - Processor, method, and data processing system employing a variable store gather window A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain ... 04/27/06 - 20060090043 - Handling of txena in an xdrtm memory controller A method, an apparatus, and a computer program are provided for controlling a transmission enable (TX_ENA) signal. In Extreme Data Rate (XDR™) Dynamic Random Access Memories (DRAMs) or XDRAMS, there is a requirement that a TX_ENA signal remain logic high for a few cycles before data transmission, and, when TX_ENA ... 03/30/06 - 20060069885 - File system with file management function and file management method The storage area of a storage unit includes a file area and temporary write area. A pair of map tables are allocated in the storage area. An update processing unit executes update of a page in a file stored in a file area by writing updated data to an unused ... 03/30/06 - 20060069884 - Universal network to device bridge chip that enables network directly attached device Network bridge circuit, logic, chip, and method that enables a host computer to access a storage device or a plurality of storage devices directly from the network. Hardware architecture includes protocol layer handler, DMA, storage device interface, command execution unit, and optional error handler. Bridge circuit logic implemented on a ... 03/30/06 - 20060069883 - Directory server and data processing method in directory server This invention is a technique to appropriately manage and use data before and after updating in a directory server. A data processing method executed by the directory server comprises: receiving first request data containing at least a first attribute value and concerning registration of an attribute into a particular entry ... 03/23/06 - 20060064555 - Systems and methods for storage modeling & costing The present invention provides systems and methods for data storage. A hierarchical storage management architecture is presented to facilitate data management. The disclosed system provides methods for evaluating the state of stored data relative to enterprise needs by using weighted parameters that may be user defined. Also disclosed are systems ... 03/02/06 - 20060047921 - Method and apparatus for managing storage used by a processor when processing instructions A method and apparatus is disclosed for managing storage used by a processor when processing instructions in which an estimate of register usage for program procedures or functions is generated and used to control the storage of the register bank in memory. ... 03/02/06 - 20060047920 - Method and apparatus for using a one-time or few-time programmable memory with a host device designed for erasable/rewriteable memory The embodiments described herein can be used to enable one-time or few-time programmable memories to work with existing consumer electronic devices (such as those that work with flash—an erasable, non-volatile memory) without requiring a firmware upgrade, thereby providing backwards compatibility while minimizing user impact. As such, these embodiments are a ... 02/23/06 - 20060041725 - Engine for comparing a key with rules having defined ranges Provided is an engine for comparing a key with rules having defined ranges. A key is received and a rule is accessed including a high and low values defining a range. The key is concurrently compared with the high and low values to determine whether the key falls within a ... 02/09/06 - 20060031643 - Implementing fifos in shared memory using linked lists and interleaved linked lists FIFOs may be implemented in shared memory using linked lists and interleaved linked lists such that any individual FIFO can dynamically use any free memory location. The system may be implemented in hardware efficiently and does not pre-allocate memory to any FIFO, so that the whole shared memory may be ... 02/02/06 - 20060026370 - Method and system for accessing indirect memories Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises instructions that create an instance of a ... 02/02/06 - 20060026369 - Store data control device and store data control method A store data control device that controls a store buffer and a write buffer that temporarily retains store data, and that executes a merging process on store data when transferring store data from the store buffer to the write buffer. The store data control device acquires a buffer state of ... 02/02/06 - 20060026368 - Storage device The present invention relates to a storage device which receives input of data of arbitrary data length, stores the data, and outputs the stored data in order of input. It provides a storage device capable of unloading data of arbitrary data length from data areas quickly. The storage device is ... 02/02/06 - 20060026367 - Storage task coordination apparatus method and system A system for automated execution of storage-related tasks includes a storage server configured to receive a storage task descriptor, initiate execution of a storage task corresponding to the storage task descriptor, and provide notification to one or more hosts in response to completion of the storage task. The storage server ... 01/26/06 - 20060020760 - Method, system, and program for storing sensor data in autonomic systems An autonomic system directed to opportunistically store captured data from at least two writer processes executing in an autonomic system. The method includes: creating a pool of storage locations in which data can be stored by the at least two writing processes, one of the at least two writer processes ... 01/19/06 - 20060015692 - Redundant controller host-side io rerouting A redundant controller storage virtualization subsystem performing host-side IO rerouting and dynamic logical media unit reassignment. In one embodiment, when a host IO request is received by a storage virtualization controller that is not a logical media unit owner of the logical media unit addressed by the IO request, the ... 01/19/06 - 20060015691 - Memory device trims Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory array, and a reference trim circuit corresponding to a portion of the memory array. The reference trim circuit is adapted to store one or ... 01/19/06 - 20060015690 - Method, system and program product for storing downloadable content on a plurality of enterprise storage system (ess) cells The present invention takes advantage of unused storage space within the ESS cells to provide for the efficient and cost effective storage of downloadable content. Specifically, the system of the present invention generally includes a download grid manager that communicates with the ESS cells. Content to be replicated to the ... 01/05/06 - 20060004972 - Semiconductor memory device and method of testing the same The invention discloses a semiconductor memory device and a method of testing the same. The semiconductor memory device comprises a memory for receiving or outputting data in response to a first clock signal; an input converting means for converting and outputting input data in response to a second clock signal; ... 01/05/06 - 20060004971 - Incremental merge methods and memory systems using the same Memory systems and methods of controlling a flash memory are provided that execute one of a plurality of merge stages of an incremental merge operation responsive to receiving a command to the flash memory. Executing one of a plurality of merge stages may include receiving a command to the flash ... 01/05/06 - 20060004970 - Programming non-volatile memory devices based on data logic values A nonvolatile memory device includes a memory cell array, a data scanning unit, and a program unit. The memory cell array includes a plurality of memory cells, where each of the memory cells is programmable to store data have a first logic value or a second logic value. The data ... 01/05/06 - 20060004969 - High-speed accessible memory featuring reduced data movement A control section includes an address information detection section detecting address information from a write command including address information, an address information storage section storing address information, and a first address determination section determining whether or not the address information detected by the address information detection section matches with the ... 01/05/06 - 20060004968 - Method and apparatus for memory compression Memory apparatus and methods for memory compression. A memory agent may comprise a compression engine to compress or decompress data in the agent without sending the data on the host memory channel. Other embodiments are described and claimed. ... 12/29/05 - 20050289304 - Control chip and method thereof and computer system utilizing the same A control chip for controlling and accessing an external memory module. The control chip comprises a terminal module and a decision unit. The terminal module is coupled to the external memory module through a memory bus for selectively matching the impedance of the memory bus. The decision unit is coupled ... 12/22/05 - 20050283579 - Arrangements storing different versions of a set of data in separate memory areas and method for updating a set of data in a memory Computer-readable medium storing a data structure for supporting persistant storage of a set of data, the data structure including: (a) at least an oldest version of the set of data in a first memory area the first memory area including at least one first tag for uniquely identifying the oldest ... 12/15/05 - 20050278490 - Memory access control apparatus and method of controlling memory access A memory interface circuit controls a memory device that inputs and outputs data in response to data strobe signals. The memory interface circuit includes an at-input selection unit selecting a data strobe signal to be received at the time of inputting the data based on information concerning the number of ... 11/24/05 - 20050262314 - System and method for circular buffer A system and method that determine whether a circular buffer is empty or full. The method may utilize two pointers, one to write data to the buffer, and one to read data from the buffer. The pointers may be initialized to point to the first location of the buffer. Each ... 11/10/05 - 20050251632 - Silicon storage media, controller and access method thereof The present invention provides a silicon storage media, a controller and an access method thereof. The silicon storage media includes a memory module and a controller. A block is designated as a basic erase/write/save unit in the memory module. The controller includes a system interface electrically coupled to the computer ... 11/03/05 - 20050246507 - Storage pre-alignment and ebcdic, ascii and unicode basic latin conversions for packed decimal data A method of pre-aligning data for storage during instruction execution improves performance by eliminating the cycles otherwise required for data alignment. The method can convert data between ASCII and Packed Decimal format, and between Unicode Basic Latin and Packed Decimal format. Conversion to Packed Decimal format is needed for decimal ... 10/20/05 - 20050235118 - Data storage circuit, data write method in the data storage circuit, and data storage device It is an object to, in a data storage circuit for storing data, provide a power saving data storage circuit and a data writing method in the data storage circuit, and further, a data storage device. Thus, in the present invention, reading out of existing data stored in a storage ... 10/06/05 - 20050223179 - Buffer device and method of operation in a buffer device An integrated circuit buffer device comprising a receiver circuit to receive control information and address information. A first interface portion provides at least a first control signal that specifies a write operation to a first memory device. The first control signal corresponds to the control information. A second interface portion ... 09/29/05 - 20050216678 - Memory hub and method for providing memory sequencing hints A memory module includes a memory hub coupled to several memory devices. The memory hub is also coupled to receive a memory packet from a system controller containing a memory hint indicative of the subsequent operation of the memory devices. The memory module uses the hint to adjust the operation ... 09/22/05 - 20050210207 - Maintenance terminal of disk array device A maintenance terminal for a disk array device is provided which can make setting of the disk array device and can easily confirm the setting contents. The maintenance terminal for the disk array device has three jumper connectors as setting terminals into which a conduction pin is inserted. The maintenance ... 09/22/05 - 20050210206 - Anticipatory power control of memory In a system in which individual memory banks may be under individual power control, a subsequent need for a memory bank that is currently in a low power state may be anticipated, so that the memory bank may be powered up in advance of when it is needed, to reduce ... 09/22/05 - 20050210205 - Method for employing memory with defective sections A method for forming a linked list with defective memory in an electronic device is disclosed. The method includes the steps of: performing at least a built-in self test (BIST) on a memory of the electronic device; and forming or updating the linked list of the electronic device according to ... 09/15/05 - 20050204103 - Split queuing Queuing operations are separated into distinct logical blocks despite the need to share information. Preparatory operations such as queue status fetching, correctness check and random early drop operation may be performed in one or more logical blocks and the completion of the queuing operation, either enqueuing, dequeuing or both, may ... 09/08/05 - 20050198448 - Self-administered shared virtual memory device, suitable for managing at least one multitrack data flow The invention concerns a device comprising a virtual RAM area (4, 5), which is reserved and dedicated to the processing of multitrack flows, comprising a switcher process (27) defining at least one memory line, and multiple flow management processes (PGF1-PGF5), creating or using at least one synchronized buffer in at ... 08/11/05 - 20050177690 - Dynamic command and/or address mirroring system and method for memory modules A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The memory devices are mounted in mirrored configuration with mirrored terminals of memory devices on opposite surfaces being interconnected. A memory hub mounted on each ... 08/04/05 - 20050172090 - Imem task index register architecture A computing system that includes a number of processing elements, a memory and a multi-task controller is disclosed. The memory has an interface that includes a task page mechanism with an index register. A portion of the multi-task controller also has a task page register for accessing the memory via ... 08/04/05 - 20050172089 - Imem ascii index registers A computing system that includes a number of processing elements, a memory and a multi-task controller. The memory is organized into a set of logical partitions. Task partitions describe a task and include task state information, task data registers and ASCII task instructions. The task state information includes a set ... 08/04/05 - 20050172088 - Intelligent memory device with wakeup feature A wakeup mechanism for computing system is disclosed. A wakeup unit connected to a host interface is configured to detect a sequence of data values and to generate the activation signal if the detected sequence matches an expected sequence of data values. First, a read by the host processor at ... 08/04/05 - 20050172087 - Intelligent memory device with ascii registers An ASCII-based processing system is disclosed. A memory is divided into a plurality of logical partitions. Each partition has a range of memory addresses and includes information associated with a particular task. Task information includes contents of task state register and one or more task data registers, with each task ... 08/04/05 - 20050172086 - Non-volatile semiconductor memory device and electric device with the same A non-volatile semiconductor memory device including: a plurality of cell arrays each having electrically rewritable and non-volatile memory cells arranged therein; a plurality of page buffers disposed in correspondence with the cell arrays respectively for reading and writing data by a page of the respective cell arrays; and a data ... 08/04/05 - 20050172085 - Intelligent memory device Coordination between multiple processors presents a set of difficult problems, since most processors are not designed for multi-processing, but for multi-tasking. Additionally, CPUs are increasingly limited by the memory bandwidth bottleneck. The iMEM architecture addresses the multi-processing problem, by simplifying processor access, and the memory bandwidth problem, by distributing intelligence ... 08/04/05 - 20050172084 - Buffer control system and method for a memory system having memory request buffers A memory controller and method for managing the issuance of read and write requests to a system memory is provided. The number of outstanding read requests and write requests issued to the system memory are separately monitored and further issuance of read and write requests to the system memory are ... 07/21/05 - 20050160241 - High performance cost optimized memory A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins. ... 07/14/05 - 20050154844 - Asynchronous communication program, asynchronous communication apparatus and asynchronous communication method When a data storage request is issued, data is stored at an address indicated by a pointer that indicates the start of a free area, and when a data fetch request is issued, data is fetched from a data storage area indicated by an oldest index. Moreover, when a condense ... 07/14/05 - 20050154843 - Method of managing a device for memorizing data organized in a queue, and associated device Method of managing a device for memorizing data organized in a queue, in which, when the queue is empty of data and receives a data read request, the read request is memorized in the queue, instead of the data usually present when the queue is not empty of data, transforming ... 07/14/05 - 20050154842 - Address control system for a memory storage device A memory storage device having an address control system is disclosed. The memory storage device includes memory cells and an address control system configured to decode a bit number which identifies a number of the memory cells which are selected in parallel. The memory cells selected in parallel correspond to ... 06/30/05 - 20050144404 - Storage control subsystem for managing logical volumes The present invention provides a storage control subsystem that facilitates logical volume access management by a host. Before copying, the host instructs a disk array device to identify the states of target logical volumes and collect information in control memory, whereupon the disk array device reads information in the control ... 06/30/05 - 20050144403 - Memory hub and method for memory system performance monitoring A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics-for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, read rate, number of read requests, write ... 06/23/05 - 20050138303 - Storage device A storage device that is detachably attachable to an information processing apparatus, comprises an IC chip; a first control unit extracting a control command for the IC chip included in a control command for the storage device from the information processing apparatus; and a second control unit performing interface conversion ... 06/23/05 - 20050138302 - Method and apparatus for logic analyzer observability of buffered memory module links Some embodiments of the invention maintain a high degree of overall logic analysis and debug capabilities while simultaneously enabling the reduction of logic analyzer design complexity. Other embodiments of the invention provide a logical analyzer interface (LAI) mode of operation to memory module buffers by adding additional LAI features to ... 06/23/05 - 20050138301 - Using a processor to program a semiconductor memory A memory programmer may be coupled through a first processor and a physical interface to a semiconductor memory to be programmed. The interface may be the same interface that allows two separate processors in a multiprocessor memory to communicate with one another in one embodiment. Thus, an independent memory bus ... 06/16/05 - 20050132152 - Method and apparatus for writing data in a medium, and method and apparatus for reading out data from a medium A method and an apparatus for writing data in a recording medium and/or reading out data from the recording medium. In the method and apparatus for reading out and writing data having a second data length unit with respect to a recording medium in which data are processed in a ... 06/16/05 - 20050132151 - Portable electronic device In a portable electronic device, pointer information used to access files which are divided into a plurality of record data areas is held for each logical channel, and when a file selection command which specifies a logical command is received from the exterior, access to the file is controlled based ... 06/16/05 - 20050132150 - Data storage systems A data storage subsystem includes a volatile memory in which stored data can be denoted as being data that should be preserved in the event of an interruption in the power supply to the volatile memory. The available capacity for such data storage is dynamically allocated between multiple firmware client ... 06/16/05 - 20050132149 - Spatial-to-temporal data translation and scheduling and control An organization of at least one content of at least one spatial data storage system is determined. A schedule of content transmission in response to the organization of the at least one content of the at least one spatial data storage device is defined. ... 06/16/05 - 20050132148 - Method and system for thread-based memory speculation in a memory subsystem of a data processing system A data processing system includes a system memory, one or more processing cores, and a memory controller that controls access to a system memory. The memory controller includes a memory speculation mechanism that stores historical information regarding prior memory accesses. In response to a memory access request, the memory controller ... 06/16/05 - 20050132147 - Method and system for supplier-based memory speculation in a memory subsystem of a data processing system A data processing system includes one or more processing cores, a system memory having multiple rows of data storage, and a memory controller that controls access to the system memory and performs supplier-based memory speculation. The memory controller includes a memory speculation table that stores historical information regarding prior memory ... 06/02/05 - 20050120186 - Memory system and process for controlling a memory component to achieve different kinds of memory characteristics on one and the same memory component According to the invention, a memory system, and a process for controlling a memory component, to achieve different kinds of memory characteristics on one and the same memory component, is provided, the process comprising the steps: Sending out a signal to select one of several possible modes for the memory ... ### FreshPatents.com Support |