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Electrical Computers And Digital Processing Systems: Memory > Storage Accessing And Control > Shared Memory Area > Prioritized Access Regulation Prioritized Access RegulationPrioritized Access Regulation patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/28/06 - 20060218358 - Enforcing strongly-ordered requests in a weakly-ordered processing system The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or ... 06/22/06 - 20060136678 - Method and system for reducing program code size In a method for reducing code size a replaceable subset of instructions at a first location within a set of instructions and a matching target subset of instructions at a second location within the set of instructions are identified. A base offset and a relative offset are determined. The base ... 05/04/06 - 20060095686 - Management of i/o operations in data storage systems The invention relates to management of I/O in data storage systems. In an embodiment, the invention provides a data storage subsystem processing I/O requests each having a priority, comprising a processor, a memory coupled to the processor, a disk array, an array controller coupled to the processor and the disk ... 03/30/06 - 20060069882 - Memory controller for processor having multiple programmable units A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory ... 03/16/06 - 20060059319 - Architecture with shared memory A system with multiple processors sharing a single memory module without noticeable performance degradation is described. The memory module is divided into n independently addressable banks, where n is at least 2 and mapped such that sequential addresses are rotated between the banks. Such a mapping causes sequential data bytes ... 11/17/05 - 20050257013 - Storage access prioritization using a data storage device Herein described is a method and system of prioritizing access to data stored in one or more data processing devices communicatively coupled to the data storage device. The method may be based on the type of data file accessed. Prioritization may be based on data pool or share names. Further, ... 11/17/05 - 20050257012 - Storage device flow control A method for allocating data write credits for a storage device includes gathering requests for the data write credits from a plurality of data sources and assembling the plurality of data sources in a prioritized list. The method also includes removing lowest priority data sources one by one from the ... 11/03/05 - 20050246505 - Efficient sharing of memory between applications running under different operating systems on a shared hardware system A system, method and computer program product for efficient sharing of memory between first and second applications running under first and second operating systems on a shared hardware system. The hardware system runs a hypervisor that supports concurrent execution of the first and second operating systems, and further includes a ... 08/04/05 - 20050172083 - Selection of a resource in a distributed computer system A method for selecting a resource from a plurality of resources includes determining a score for that resource on the basis of a stochastic property of that resource. An interval corrsesponding to that resource is then defined to have an extent that depends on the score. A particular resource is ... 06/30/05 - 20050144401 - Multiprocessor mobile terminal with shared memory arbitration In a mobile terminal including at least two CPUs and a shared memory resource, a CPU executing real-time code has priority access to the memory over a CPU executing non-real-time code. In one embodiment, real-time code and non-real-time code are located in separate regions of logical memory, and a memory ... 06/23/05 - 20050138300 - Prioritization of real time / non-real time memory requests from bus compliant devices One or more methods and systems of prioritizing access of physical memory space to bus compliant devices in a computing device is presented. Prioritization is based on real time or non-real time device functionality. In one embodiment, the method of accessing physical memory space for use by a bus compliant ... 06/16/05 - 20050132146 - Arbiter capable of improving access efficiency of multi-bank memory device, memory access arbitration system including the same, and arbitration method thereof Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the arbiter detects requests that are not included in a busy bank, and allows the requests corresponding to a bank receiving the ... ### FreshPatents.com Support |