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Electrical Computers And Digital Processing Systems: Memory > Storage Accessing And Control > Shared Memory Area > Simultaneous Access Regulation Simultaneous Access RegulationSimultaneous Access Regulation patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236040 - Multiprocessor system for preventing starvation in case of occurring address competition and method thereof A case occurs in which a preceding transaction to be retried cannot be retried as a result of snooping. If the snoop result is waited for so that a retry decision may be made after the result of snoop has been obtained, latency is prolonged to urge the pipeline to ... 09/28/06 - 20060218357 - Storage system A storage system coupled to host computers, includes: a plurality of disk drives; a plurality of processors, each controlling data reception and data transmission between the host computers and the disk drives; a shared memory for storing control information; and a plurality of shared memory control units provided for a ... 09/28/06 - 20060218356 - Adaptive granularity refinement in detecting potential data races A method and apparatus are provided for detecting data races that overcome the limitations of the prior art. In some embodiments, this is accomplished by detecting a first access to an object, determining whether the first access is associated with a suspicious pattern, automatically refining a pattern detection granularity from ... 09/21/06 - 20060212663 - Inter-cluster communication module using the memory access network An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue a load instruction and some clusters issue a store instruction of an identical memory address concurrently, the controller controls the switch ... 08/10/06 - 20060179258 - Method for detecting address match in a deeply pipelined processor design A method, apparatus and algorithm for quickly detecting an address match in a deeply pipelined processor design in a manner that may be implemented using a minimum of physical space in the critical area of the processor. The address comparison is split into two parts. The first part is a ... 08/03/06 - 20060174070 - Memory hub bypass circuit and method A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurality of memory devices. ... 07/20/06 - 20060161738 - Predicting contention in a processor In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction, which may be based on multiple independent predictions. In one embodiment, the operation may be optimized if ... 05/18/06 - 20060106997 - Bridge permitting access by multiple hosts to a single ported storage drive A bridge comprises an interface to a plurality of hosts, an interface to a single-ported storage drive and arbitration logic. The arbitration logic controls and permits concurrent access by the hosts to the single-ported storage drive so that the bridge need not store read or write data being received from ... 05/18/06 - 20060106996 - Updating data shared among systems Provided are a method, system and program for updating data shared among systems. A first and second systems maintain a first and second copies, respectively, of shared data stored in a storage device. The first system obtains a first lock to the shared data, wherein the first lock applies to ... 05/04/06 - 20060095685 - System and method to coordinate access to a sharable data structure using deferred cycles In at least some embodiments, a system comprises a plurality of requesters and control logic. The requestors are each capable of accessing a sharable data structure. The control logic causes a request for access to the sharable data structure to be deferred to permit only one requestor at a time ... 04/06/06 - 20060075197 - Multi-processor system Data transmission for writing data into a shared memory is performed by a high-speed dedicated line provided between each processor and the shared memory. When a processor performs writing to a shared memory space, the processor notifies an update notification bus corresponding to the conventional global bus, to which address ... 03/30/06 - 20060069881 - Shared memory access control apparatus A main CPU and a sub-CPU share a single port memory. In the single port memory in which a predetermined time has elapsed after the main CPU ends access to the single port memory, the sub-CPU sets a bus right of the single port memory to itself to access the ... 03/02/06 - 20060047919 - Atomic read/write support in a multi-module memory configuration Efficient transfer of data to and from random access memory is described. Multiple request sources and a memory system comprise memory modules having memory banks, each bank containing rows of data. The retrieval comprises transferring all data pursuant to a given request by one source before any data is transferred ... 01/12/06 - 20060010298 - Device for controlling the flow of processes in a processor system In a device for controlling the flow of processes in a processor system, a processing unit (1) accessing at least one memory and the at least one memory (2) have a process management device (8) between them which allows the processor (1) to access only address ranges and/or hardware macros ... 01/12/06 - 20060010297 - Atomically updating 64 bit fields in the 32 bit aix kernel A method, system, and computer instructions for atomically updating 64-bit fields in the 32-bit AIX kernel, wherein the underlying hardware's 64-bit capable instructions are used to construct an atomic primitive. If a data request applies to the 32-bit kernel on 64-bit hardware execution environment, a load and reserve instruction sets ... 11/24/05 - 20050262313 - Modified computer architecture with coordinated objects The present invention discloses a modified computer architecture (50, 71, 72) which enables an applications program (50) to be run simultaneously on a plurality of computers (M1, . . . Mn). Shared memory at each computer is updated with amendments and/or overwrites so that all memory read requests are satisfied ... 11/03/05 - 20050246504 - Reactive deadlock management in storage area networks Systems and methods in accordance with various embodiments can detect and alleviate potential or actual deadlock of a storage switch or storage area network when attempting to write data to a mirrored virtual target. In accordance with one embodiment, a timer is started when a storage switch routes a write ... 10/06/05 - 20050223178 - Delegated write for race avoidance in a processor In a system including multiple-slice processors and memories, a synchronization unit with race avoidance capability includes a delegated write engine that receives data and memory address information from the processors and writes data to the memory as a delegate for the processors. ... 09/29/05 - 20050216677 - Memory arbitration system and method having an arbitration packet protocol A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory ... 09/15/05 - 20050204102 - Register access protocol for multi processor systems The present invention provides shared registers in a multi-processor system with a contention management protocol when a register is simultaneously accessed by more than one processor. Each register includes access protocol and data. The access protocol includes an access type for each processors and arbitration priority. The configurable access type ... 06/16/05 - 20050132145 - Contingent processor time division multiple access of memory in a multi-processor system to allow supplemental memory consumer access Mechanisms in which a memory controller efficiently manages time-division multiple access to system memory for multiple processors and for one or more other memory consumers present in the system. At least one processor is guaranteed access to system memory during its time slot in a memory access cycle, while at ... ### FreshPatents.com Support |