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Electrical Computers And Digital Processing Systems: Memory > Storage Accessing And Control > Shared Memory Area > Multiport Memory Multiport MemoryMultiport Memory patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.08/10/06 - 20060179257 - Apparatus and method for providing multiple reads/writes using a 2read/2write register file array An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each ... 07/27/06 - 20060168406 - Balanced bitcell design for a multi-port register file In a multi-port register file of a storage unit within a processor, an improved bitcell design for storing a data bit is disclosed. The bitcell comprises a first set of read bitlines having a first load and a second set of read bitlines having a second load, in which the ... 07/27/06 - 20060168405 - Sharing memory among multiple information channels Memory is shared among multiple information channels, which may be of particular use for storing streams of packets. Memory allocation information is maintained which can be used to identify the current number of memory segments (e.g., some definable amount of memory) allocated for each of the multiple channels as well ... 07/13/06 - 20060155938 - Shared-memory switch fabric architecture A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive ... 06/29/06 - 20060143410 - Method and related apparatus for realizing two-port synchronous memory device Method and related apparatus for realizing a two-port synchronous memory device with a single-port memory. Clock-triggered two-port synchronous memory device can synchronously receive reading and writing commands within a clock period to simultaneous execute these two commands, while a single port memory must execute a single reading and writing command ... 06/08/06 - 20060123202 - Memory based cross compare for cross checked systems A cross compare solution running in a multiprocessor configuration, using a multi-port RAM with built-in logic. This provides for a fast and simple data cross compare medium. The multi-port RAM unit can be plugged into the motherboard of the main processor unit, requiring no external hardware or wiring. A method ... 03/30/06 - 20060069880 - Apparatus for controlling access, by processing devices, to memories in an embedded system The present invention provides an apparatus for controlling access, by processing devices to memories in an embedded system, with the apparatus being arranged between the processing devices and the memories, and with the apparatus independently moving data between the memories and between the memories and internal memories in the processing ... 03/23/06 - 20060064553 - Data processing apparatus and system and method for controlling memory access A data processor comprises a memory having storage elements arranged in columns and a number of column decoders, each having a memory access port. The data processor has a plurality of processing elements, and each of the memory ports is coupleable to at least a respective one of the processor ... 12/01/05 - 20050268050 - Multi-port memory device providing protection signal A multi-port memory device may provide a protection signal. The multi-port memory device may generate at least one protection signal in response to a bank address signal, in order to control access to the a memory bank, and to suppress access and/or memory collision. ... 12/01/05 - 20050268049 - Dynamic memory management The present invention relates to a memory management system for allocating memory in a memory space according to amounts of memory requested by a client, said memory space comprises a number of equally sized containers, and at least some of said containers comprise a number of equally sized sub containers. ... 10/20/05 - 20050235117 - Memory with single and dual mode access The invention relates to a memory unit with at least two memory areas for storing data, first terminals for accessing data within the memory areas, and second terminals for accessing data within the memory areas. To provide multi-purpose access to the memory, the memory unit provides at least two access ... 09/15/05 - 20050204101 - Partial dual-port memory and electronic device using the same A partial dual-port memory used for an electronic device such as a mobile phone includes a storage area with a given capacity. The storage area has a first area accessed only by a first processor, a second area accessed only by a second processor, and a common area having two ... 09/15/05 - 20050204100 - Flexible multi-area memory and electronic device using the same A flexible multi-area memory used for an electronic device such as a mobile phone includes a storage area with a given capacity. The storage area has a first area accessed only by a first processor, a second area accessed only by a second processor, and a common area shared by ... 09/08/05 - 20050198446 - Create virtual track buffers in nvs using customer segments to maintain newly written data across a power loss A method for storing customer data at a non-volatile storage (NVS) at a storage server. A track buffer is maintained for identifying first and second sets of segments that are allocated in the NVS. A flag in the track buffer identifies which of the first and second sets of segments ... 09/01/05 - 20050193178 - Systems and methods for flexible extension of sas expander ports A multi-chip module (MCM) designed using standard die SAS expander components for rapidly designing a customized SAS expander having a predetermined number of ports. A number of standard expander die circuit components are selected and disposed on a MCM design. Each expander die circuit has a predetermined number of internal ... 08/11/05 - 20050177689 - Programmed access latency in mock multiport memory A computer memory arrangement comprises a first plurality of input port facilities (17-19) that are collectively coupled through a first router facility (32) to selectively feed a second plurality of memory modules (20-24). It furthermore comprises an output port facility that is collectively fed by said second plurality of memory ... 07/28/05 - 20050166021 - Pseudo multiport data memory has stall facility A computer memory arrangement comprises a first plurality of input port facilities (17-19) that are collectively coupled through a first router facility (32) to selectively feed a second plurality of memory modules (20-24). It furthermore comprises an output port facility that is fed collectively by the second plurality of memory ... ### FreshPatents.com Support |