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Electrical Computers And Digital Processing Systems: Memory > Storage Accessing And Control > Hierarchical Memories > Caching > Coherency > Snooping SnoopingSnooping patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/12/06 - 20060230239 - Method and apparatus for detecting a cache wrap condition A method and apparatus for detecting a cache wrap condition in a computing environment having a processor and a cache. A cache wrap condition is detected when the entire contents of a cache have been replaced, relative to a particular starting state. A set-associative cache is considered to have wrapped ... 10/05/06 - 20060224840 - Method and apparatus for filtering snoop requests using a scoreboard An apparatus for implementing snooping cache coherence that locally reduces the number of snoop requests presented to each cache in a multiprocessor system. A snoop filter device associated with a single processor includes one or more “scoreboard” data structures that make snoop determinations, i.e., for each snoop request from another ... 10/05/06 - 20060224839 - Method and apparatus for filtering snoop requests using multiple snoop caches A method and apparatus for implementing a snoop filter unit associated with a single processor in a multiprocessor system. The snoop filter unit has a plurality of ports, each port receiving snoop requests from exactly one dedicated source. Associated with each port is a snoop cache filter that processes each ... 10/05/06 - 20060224838 - Novel snoop filter for filtering snoop requests A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having ... 10/05/06 - 20060224837 - Method and apparatus for filtering snoop requests in a point-to-point interconnect architecture A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having ... 10/05/06 - 20060224836 - Method and apparatus for filtering snoop requests using stream registers A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having a local cache memory associated therewith. A snoop filter device is associated with each processing unit and includes at least one snoop filter primitive implementing filtering method based on ... 10/05/06 - 20060224835 - Snoop filtering system in a multiprocessor system A system and method for supporting cache coherency in a computing environment having multiple processing units, each unit having an associated cache memory system operatively coupled therewith. The system includes a plurality of interconnected snoop filter units, each snoop filter unit corresponding to and in communication with a respective processing ... 09/21/06 - 20060212660 - Method and an apparatus to reduce network utilization in a multiprocessor system A method and an apparatus to reduce network utilization for source-based snoopy cache coherent protocols have been disclosed. In one embodiment, the method includes receiving at a first processor an invalidating snoop with respect to a physical address of a portion of a memory in a multiprocessor system from a ... 09/07/06 - 20060200633 - Address snoop method and multi-processor system Address snoop methods and multi-processor systems to enable easy implementation of a large number of I/O blocks in the multi-processor system, independently of processor blocks, and to prevent the upper limit of the performance of the multi-processor system from deteriorating (prevent latency from increasing). An address snoop method for a ... 08/17/06 - 20060184749 - Reducing number of rejected snoop requests by extending time to respond to snoop request A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon ... 08/17/06 - 20060184748 - Reducing number of rejected snoop requests by extending time to respond to snoop request A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop ... 08/17/06 - 20060184747 - Bandwidth of a cache directory by slicing the cache directory into two smaller cache directories and replicating snooping logic for each sliced cache directory A cache, system and method for improving the snoop bandwidth of a cache directory. A cache directory may be sliced into two smaller cache directories each with its own snooping logic. By having two cache directories that can be accessed simultaneously, the bandwidth can be essentially doubled. Furthermore, a “frequency ... 08/17/06 - 20060184746 - Reducing number of rejected snoop requests by extending time to respond to snoop request A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. The snoop request is entered in the first available latch of the stall/reorder unit unless the stall/reorder unit is full in which case the ... 08/10/06 - 20060179254 - Data processing system, method and interconnect fabric supporting destination data tagging A data processing system includes a plurality of communication links and a plurality of processing units including a local master processing unit. The local master processing unit includes interconnect logic that couples the processing unit to one or more of the plurality of communication links and an originating master coupled ... 08/10/06 - 20060179253 - Data processing system, method and interconnect fabric that protect ownership transfer with a protection window extension A data processing system includes a memory system, a plurality of masters that issue requests for access to memory blocks within the memory system, a plurality of snoopers that provide partial responses to requests by the masters, and response logic that generates combined responses for the requests in response to ... 08/03/06 - 20060174069 - System and method for snooping cache information using a directory crossbar A system and method for maintaining coherency in a symmetric multiprocessing (SMP) system are disclosed. Briefly described, in architecture, one exemplary embodiment comprises a first crossbar coupled to a plurality of local processors; a second crossbar coupled to at least one remote processor; and at least one crossbar directory that ... 07/27/06 - 20060168404 - Memory control apparatus and method A data storage control apparatus and method for reduction of traffic of an interconnect occurring in the timing of a cache miss within a CPU. The apparatus and method are realized by utilizing, as a response to the read request from the CPU, data tags DTAGs used for management of ... 06/29/06 - 20060143409 - Method and apparatus for providing a low power mode for a processor while maintaining snoop throughput A method and apparatus for providing a low power mode for a processor while maintaining snoop throughput are disclosed. In one embodiment, an apparatus includes a cache, a processor, and a frequency controller. The frequency controller is to operate the apparatus in a low power mode in which the operating ... 06/01/06 - 20060117149 - Information processing system, system control apparatus, and system control method A system control apparatus and method capable of increasing the possibility of recovery from a synchronization error in snooping between system controllers are provided. The system control apparatus has a local port that holds a memory access request received externally and reoutputs it in response to an error retry instruction. ... 06/01/06 - 20060117148 - Preventing system snoop and cross-snoop conflicts Preventing cache conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to prevent cache conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches. ... 05/18/06 - 20060106995 - Methods to maintain triangle ordering of coherence messages We present a triangle ordering mechanism that maintains triangle ordering of coherence messages in SMP systems. If cache A sends a multicast message to caches B and C, and if cache B sends a message to cache C after receiving and processing the multicast message from cache A, the triangle ... 05/04/06 - 20060095684 - Scope-based cache coherence With scope-based cache coherence, a cache can maintain scope information for a memory address. The scope information specifies caches in which data of the address is potentially cached, but not necessarily caches in which data of the address is actually cached. Appropriate scope information can be used as snoop filters ... 04/27/06 - 20060090041 - Apparatus for controlling a multi-processor system, scalable node, scalable multi-processor system, and method of controlling a multi-processor system An apparatus for controlling a multi-processor system comprises: a plurality of local ports that holds a data request made from the node; a local snoop unit that performs a local snoop on the requests held in the local ports; a broadcast queue that broadcasts the request to the other nodes ... 04/20/06 - 20060085606 - Method and related apparatus for internal data accessing of computer system Method and related apparatus for internal data accessing of a computer system. In a computer system, a peripheral can issue accessing requests for system memory space with or without snooping the central processing unit (CPU). While serving a peripheral of single virtual channel utilizing a chipset supporting multiple virtual channels, ... 03/23/06 - 20060064552 - Cache memory and method for handling effects of external snoops colliding with in-flight operations internally to the cache A cache memory that completes an in-flight operation with another cache that collides with a snoop operation, rather than canceling the in-flight operation. Operations to the cache comprise a query pass and one or more finish passes. When the cache detects a snoop query intervening between the query pass and ... 03/02/06 - 20060047918 - Information processing apparatus, system controller, local snoop control method, and local snoop control program recorded computer-readable recording medium The present invention relates to an information processing apparatus equipped with a plurality of storage units and a plurality of system controllers sharing communication control on the plurality of storage units. For shortening the processing time needed for a memory access request, each of the plurality of system controllers includes ... 03/02/06 - 20060047917 - Method and apparatus for modifying an information unit using an atomic operation A system and method for modifying an information unit, the method includes the following stages: (i) receiving, over a first bus, a request to initiate a snooping type atomic operation associated with at least one information unit located at a first address of a memory module; (ii) providing the information ... 10/27/05 - 20050240736 - System and method for coherency filtering Systems and methods for coherency filtering are disclosed. A system may comprise a coherency filter that provides information identifying a coherency domain for data in an associated address space based on an identifier for the data. A snoop engine is configured to snoop for the data in the identified coherency ... 08/18/05 - 20050182907 - Cache residence prediction The present invention proposes a novel cache residence prediction mechanism that predicts whether requested data of a cache miss can be found in another cache. The memory controller can use the prediction result to determine if it should immediately initiate a memory access, or initiate no memory access until a ... 07/28/05 - 20050166020 - Methods and apparatus for cache intervention Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state and/or a modified state, without asserting a hit-modified signal line, are provided. In one example, a first cache holds the memory block prior to the transfer. When a processor ... 07/21/05 - 20050160240 - System and method for blocking data responses Systems and methods are disclosed for blocking data responses. One system includes a target node that, in response to a source broadcast request for requested data, provides a response that includes a copy of the requested data. The target node also provides a blocking message to a home node associated ... 07/21/05 - 20050160239 - Method for supporting improved burst transfers on a coherent bus In a multiprocessor system, comprising master and slave processors, a cache coherency controller, and address concentration devices; a method for improving coherent data transfers is described. A command transaction is generated, and a subsequent command from an initiator. Tags added to the responses or further request responses, stream on high-speed ... ### FreshPatents.com Support |