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Electrical Computers And Digital Processing Systems: Memory > Storage Accessing And Control > Hierarchical Memories > Caching > Coherency > Access Control Bit Access Control BitAccess Control Bit patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/28/06 - 20060218355 - Multi-process support with data atomicity guaranteed with shared register of data of control signals A method of, shared register system and system for controlling access to a register are described. The shared register stores a plurality of bits including control and data bits. An access signal and a combined signal including a control portion and a data portion are received and the data portion ... 07/13/06 - 20060155937 - System for selectively enabling data tables A method of selectively enabling data tables includes accessing data from a first data table, downloading a second data table, upon reaching a predetermined criteria, comparing corresponding data from the first and second data tables each time data is accessed from the first data table, prompting a user to accept ... 07/13/06 - 20060155936 - Efficient memory update process for on-the-fly instruction translation for well behaved applications executing on a weakly-ordered processor A multiprocessor data processing system (MDPS) with a weakly-ordered architecture providing processing logic for substantially eliminating issuing sync instructions after every store instruction of a well-behaved application. Instructions of a well-behaved application are translated and executed by a weakly-ordered processor. The processing logic includes a lock address tracking utility (LATU), ... 06/29/06 - 20060143408 - Efficient usage of last level caches in a mcmp system using application level configuration This disclosure presents an architectural mechanism which allows a caching bridge to efficiently store data either inclusively or exclusively based upon information configured by an application. An INC bit is set for each access to a page table that indicates whether the data is shared or not shared by a ... 06/01/06 - 20060117147 - Managing multiprocessor operations In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in ... 05/25/06 - 20060112238 - Techniques for pushing data to a processor cache A technique to write data to a processor cache without using intermediate memory storage. More particularly, embodiments of the invention relate to various techniques for writing data from a bus agent to a processor cache without having to first write the data to memory and then having the processor read ... 04/06/06 - 20060075195 - Methods, systems, and computer pogram products for tracking ownership of memory in a data processing system through use of a memory monitor Ownership of a memory unit in a data processing system is tracked by assigning an identifier to each software component in the data processing system that can acquire ownership of the memory unit. An ownership variable is updated with the identifier of the software component that acquires ownership of the ... 03/23/06 - 20060064551 - Cache lock mechanism with speculative allocation A method and apparatus to speculatively allocate a combinable store request buffer for a cache lock operation by setting an extended lock indicator. The store request buffer is speculatively allocated and the load-lock micro-operation associated with the cache lock operation is sent to a replay loop. During the replay window, ... 03/16/06 - 20060059317 - Multiprocessing apparatus The multiprocessing apparatus of the present invention is a multiprocessing apparatus including a plurality of processors, a shared bus, and a shared bus controller, wherein each of the processors includes a central processing unit (CPU) and a local cache, each of the local caches includes a cache memory, and a ... 03/09/06 - 20060053258 - Cache filtering using core indicators A caching architecture within a microprocessor to filter core cache accesses. More particularly, embodiments of the invention relate to a technique to manage transactions, such as snoops, within a processor having a number of processor core caches and an inclusive shared cache. ... 12/15/05 - 20050278487 - Efficient parallel bitwise sweep during garbage collection A method, system, and program for efficient parallel bitwise sweeps of larger objects during garbage collection are provided. During a bitwise sweep, a helper thread scans a mark vector looking for a consecutive sequence of unmarked bits of a sufficient length following a marked bit. Once a consecutive sequence of ... 11/10/05 - 20050251631 - Coherent shared memory processing system A shared memory system includes a plurality of processing nodes and a packetized input/output link. Each of the plurality of processing nodes includes a processing resource and memory. The packetized I/O link operably couples the plurality of processing nodes together. One of the plurality of processing nodes is operably coupled ... 10/06/05 - 20050223177 - Store performance A store operation architecture in which store operation latency and read-for-ownership (RFO) throughput are improved. Embodiments of the invention relate to a method and apparatus to improve store performance in a microprocessor by allowing out-of-order issuance of RFO operations and more efficiently using the store buffer latency periods. ... 09/29/05 - 20050216676 - Semiconductor memory device and method of entry of operation modes thereof If read cycles for plural addresses are continued, then a request for entry of operation mode is accepted (steps S1 and S2). In write cycles following to those read cycles, an operation mode to be entered is decided based on data externally designated, wherein in the first write cycle, the ... 09/22/05 - 20050210204 - Memory control device, data cache control device, central processing device, storage device control method, data cache control method, and cache control method A central processing device includes a plurality of sets of instruction processors that concurrently execute a plurality of threads and primary data cache devices. A secondary cache device is shared by the primary data cache device belonging to different sets. The central processing device also includes a primary data cache ... 09/08/05 - 20050198442 - Conditionally accessible cache memory A cache memory has a conditional access mechanism, operated by a locking condition. The conditional access mechanism uses the locking condition to implement conditional accessing of the cache memory. ... 09/01/05 - 20050193177 - Selectively transmitting cache misses within coherence protocol Selectively transmitting cache misses within multiple-node shared-memory systems employing coherence protocols is disclosed. A cache-coherent system includes a number of nodes employing a coherence protocol to maintain cache coherency, as well as memory that is divided into a number of memory units. There is a cache within each node to ... 08/25/05 - 20050188160 - Method and apparatus for maintaining coherence information in multi-cache systems A method and apparatus for maintaining coherence information in multi-cache systems is described herein. In one embodiment, the apparatus includes an Ingrained Sharing Directory Cache (ISDC) to store state information about recent copies of local memory blocks. The ISDC is adapted to receive Ingrained Sharing Directory Storage (ISDS) requests and ... 08/11/05 - 20050177688 - Cache coherence protocol for a multiple bus multiprocessor system A computer system maintains a list of tags (called a Global Ownership Tag List (GOTL)) for all the cache lines in the system that are owned by a cache. The GOTL is used for cache coherence. There may be one central GOTL. Alternatively, the GOTL may be distributed, so that ... 07/21/05 - 20050160238 - System and method for conflict responses in a cache coherency protocol with ordering point migration A system comprises a first node that provides a source broadcast request for data. The first node is operable to respond in a first manner to other source broadcast requests for the data while the source broadcast for the data is pending at the first node. The first node is ... 07/21/05 - 20050160237 - System and method for creating ordering points A system comprises a first node operative to provide a source broadcast requesting data. The first node associates an F-state with a copy of the data in response to receiving the copy of the data from memory and receiving non-data responses from other nodes in the system. The non-data responses ... 07/14/05 - 20050154840 - Cache line ownership transfer in multi-processor computer systems Transferring cache line ownership between processors in a shared memory multi-processor computer system. A request for ownership of a cache line is sent from a requesting processor to a memory unit. The memory unit receives the request and determines which one of a plurality of processors other than the requesting ... 06/30/05 - 20050144400 - Hierarchical virtual model of a cache hierarchy in a multiprocessor system The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some ... 06/30/05 - 20050144399 - Multiprocessor system, and consistency control device and consistency control method in multiprocessor system A multiprocessor system with cells having a plurality of CPUs sharing a memory and a consistency control device connected through a network, in which the consistency control device includes a request unit which issues an access request and a speculative access request, a home unit which receives an access request ... 06/30/05 - 20050144398 - Decoupling request for ownership tag reads from data read operations Embodiments of the present invention relate to cache coherency. In an embodiment of the invention, a cache includes one or more cache lines. A store pipeline may retrieve a tag associated with one of the cache lines. The data associated with the cache line may not retrieved and the cache ... 06/16/05 - 20050132144 - Striping across multiple cache lines to prevent false sharing A method and system for striping across multiple cache lines to prevent false sharing. A first descriptor to correspond to a first data block is created. The first descriptor is placed in a descriptor ring according to a striping policy to prevent false sharing of a cache line of the ... 06/16/05 - 20050132143 - Intent seizes in a multi-processor environment A method, apparatus, system, and signal-bearing medium that in an embodiment use a requested address for an intent seize and a processor associated with the intent seize to determine a hash table entry. If the requested address is not found in the hash table, all hash tables for all processors ... ### FreshPatents.com Support |