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Electrical Computers And Digital Processing Systems: Memory > Storage Accessing And Control > Hierarchical Memories > Caching > Coherency CoherencyCoherency patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236038 - Hierarchical virtual model of a cache hierarchy in a multiprocessor system The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some ... 10/19/06 - 20060236037 - Cache memory, processing unit, data processing system and method for assuming a selected invalid coherency state based upon a request source At a first cache memory affiliated with a first processor core, an exclusive memory access operation is received via an interconnect fabric coupling the first cache memory to second and third cache memories respectively affiliated with second and third processor cores. The exclusive memory access operation specifies a target address. ... 10/12/06 - 20060230238 - Multi-node communication system and method of requesting, reporting and collecting destination-node-based measurements and route-based measurements A multi-node communication system and method used to request, report and collect destination-node-based measurements and route-based measurements is disclosed. The communication system may be a mesh network including a plurality of mesh points (MPs). In one embodiment, a destination-node-based measurement request is sent to one or more destination nodes via ... 10/12/06 - 20060230237 - Method and system for maintaining cache coherence of distributed shared memory system A distributed shared memory system includes a plurality of nodes. Each of the nodes includes a plurality of shared multiprocessors. Each of the shared multiprocessors includes a processor, a shared cache, and a memory. Each of the nodes includes a coherence maintaining unit that maintains cache coherence based on a ... 10/05/06 - 20060224833 - Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state In response to a master receiving a memory access request indicating a target address, the master accesses a first cache directory of an upper level cache of a cache hierarchy. In response to the target address being associated in the first cache directory with an entry having a valid address ... 09/28/06 - 20060218353 - Method and apparatus for implementing path-based traffic stream admission control in a wireless mesh network A method and apparatus for implementing path-based traffic stream (TS) admission control in a wireless mesh network having a distributed and/or centralized admission control architecture is disclosed. When the wireless mesh utilizes distributed admission control architecture, a source mesh point (S.MP) transmits a request for TS admission requiring certain resources/quality ... 09/21/06 - 20060212659 - Systems and arrangements for promoting a line from shared to exclusive in a cache Systems and arrangements promoting a line from shared to exclusive in cache are contemplated. Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. ... 09/07/06 - 20060200632 - Selectively unmarking load-marked cache lines during transactional program execution One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads. During operation, the system encounters a release instruction during transactional execution of a block ... 08/17/06 - 20060184744 - Method and apparatus for implementing a combined data/coherency cache A method and apparatus for implementing a combined data/coherency cache for a shared memory multi-processor. The combined data/coherency cache includes a system cache with a number of entries. The method includes building a system cache directory with a number of entries equal to the number of entries of the system ... 08/10/06 - 20060179249 - Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memory A cache coherent data processing system includes a memory and at least first and second coherency domains that each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation targeting a request address ... 08/10/06 - 20060179248 - Data processing system and method for efficient storage of metadata in a system memory A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory ... 08/10/06 - 20060179247 - Data processing system and method for efficient communication utilizing an ig coherency state A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The ... 08/10/06 - 20060179246 - Data processing system and method for efficient coherency communication utilizing coherency domain indicators In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master ... 08/10/06 - 20060179245 - Data processing system and method for efficient communication utilizing an tn and ten coherency states A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory ... 08/10/06 - 20060179244 - Cache memory, processing unit, data processing system and method for filtering snooped operations A cache coherent data processing system includes at least a first cache memory supporting a first processing unit and a second cache memory supporting a second processing unit. The first cache memory includes a cache array and a cache directory of contents of the cache array. In response to the ... 08/10/06 - 20060179243 - Data processing system and method for efficient coherency communication utilizing coherency domains In a cache coherent data processing system including at least first and second coherency domains, a master performs a first broadcast of an operation within the cache coherent data processing system that is limited in scope of transmission to the first coherency domain. The master receives a response of the ... 08/10/06 - 20060179242 - Data processing system and method for handling castout collisions A data processing system includes a memory controller of a system memory that receives first and second castout operations both specifying a same address. In response to receiving said first and second castout operations, the memory controller performs a single update to the system memory. ... 08/10/06 - 20060179241 - Data processing system and method for predictively selecting a scope of broadcast of an operation A cache coherent data processing system includes at least first and second coherency domains coupled for communication. The first and second coherency domains each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an ... 07/27/06 - 20060168402 - Data coherence system A data coherence system includes a generation number written to a data track of a logical sub-system. The generation number is compared to a corresponding generation number in a processing device when it is initialized. If the two generations numbers are the same, the generation numbers are incremented and saved. ... 07/13/06 - 20060155935 - System and method for maintaining cache coherency in a shared memory system A data processing system having shared memory accessible through a transaction-based bus mechanism. A plurality of system components, including a central processor, are coupled to the bus mechanism. The bus mechanism includes a cache coherency transaction within its transaction set. The cache coherency transaction comprises a request issued by one ... 07/06/06 - 20060149905 - Service system for providing context information based on ubiquitous sensor network and method thereof Provided is a service system for providing context information based on a ubiquitous sensor network and a method thereof. The context information providing service system includes: a sensing block for collecting context information of each user; an intermediating block for changing the user context information transmitted from the sensing block ... 06/29/06 - 20060143405 - Data processing device A data processor has a central processing unit and a plurality of logical blocks (1104) to be connected to the central processing unit, and the central processing unit sets a predetermined logical block to be a control object based on a result of decode of a predetermined instruction code (CBP) ... 06/29/06 - 20060143404 - System and method for cache coherency in a cache with different cache location lengths A system and method for the design and operation of a cache system with differing cache location lengths in level one caches is disclosed. In one embodiment, each level one cache may include groups of cache locations of differing length, capable of holding portions of a level two cache line. ... 06/29/06 - 20060143403 - Early coherency indication for return data in shared memory architecture In a shared memory architecture, early coherency indication is used to notify a communications interface, prior to the data for a memory request is returned, and prior to updating a coherency directory in response to the memory request, that the return data can be used by the communications interface when ... 06/29/06 - 20060143402 - Mechanism for processing uncacheable streaming data In one embodiment, a buffer is presented. The buffer comprises a type designator to designate that the buffer is a streaming read buffer, and a plurality of use designators to indicate whether data within the buffer has been used. The data within the buffer is an uncacheable memory type, such ... 06/08/06 - 20060123199 - System and method for optimistic caching Transactions are granted concurrent access to a data item through the use of an optimistic concurrency algorithm. Each transaction gets its own instance of the data item, such as in a cache or in an entity bean, such that it is not necessary to lock the data. The instances can ... 06/01/06 - 20060117146 - Cache for an enterprise software system Techniques are described for caching data from a software system, such as an enterprise software system. The techniques may be applied to a computing device connected to the software system via a network. In one example, the cache comprises an elegant, file-based cache that includes an object store that stores ... 05/25/06 - 20060112235 - Matching memory transactions to cache line boundaries In general, in one aspect, the disclosure describes a method that includes generating multiple cache line accesses to multiple respective cache lines of a cache as required to satisfy an access to data specified by a single instruction of a processing element specifying an access to data. ... 05/18/06 - 20060106992 - Distributed shared i/o cache subsystem A method and system for a decentralized distributed storage data system. A plurality of central processors each having a cache may be directly coupled to a shared set of data storage units. A high speed network may be used to communicate at a physical level between the central processors. A ... 05/04/06 - 20060095683 - Memory system and method for controlling the same, and method for maintaining data coherency A memory system including a bus 10, 11, a memory 17, a memory controller 16, a first device 13 having a cache, and a second device 15, all connected to the bus, wherein the memory controller includes a buffer 20 for temporarily storing cache data and write data that the ... 05/04/06 - 20060095682 - High-performance lock management for flash copy in n-way shared storage systems A method, system, and machine-readable medium for providing high-performance lock management for a flash copy image of a region of data in N-way shared storage systems is disclosed. According to one embodiment, a data processing system is provided which comprises a cache to store a copy of metadata specifying a ... 04/20/06 - 20060085605 - Processor, data processing system and method for synchronzing access to data in shared memory A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit. The instruction execution unit, responsive to receipt of a load-reserve instruction from ... 04/20/06 - 20060085604 - Processor, data processing system and method for synchronizing access to data in shared memory A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit coupled to the instruction sequencing unit that concurrently executes multiple threads of ... 04/20/06 - 20060085603 - Processor, data processing system and method for synchronzing access to data in shared memory A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to determine a store target address, a store queue that, following execution of the store-conditional ... 04/13/06 - 20060080513 - Low latency coherency protocol for a multi-chip multiprocessor system Methods and apparatus for reducing the amount of latency involved when accessing, by a remote device, data residing in a cache of a processor are provided. For some embodiments, virtual channels may be utilized to conduct request/response transactions between the remote device and processor that satisfy a set of associated ... 04/13/06 - 20060080512 - Graphics processor with snoop filter Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. The remote device may include coherency logic, referred to herein as a snoop filter, designed to filter memory access requests that do not require bus commands to ... 04/13/06 - 20060080511 - Enhanced bus transactions for efficient support of a remote cache directory copy Methods and apparatus are provided that may be utilized to maintain a copy of a processor cache directory on a remote device that may access data residing in a cache of the processor. Enhanced bus transactions containing cache coherency information used to maintain the remote cache directory may be automatically ... 03/23/06 - 20060064550 - Storage device and write access processing method for storage device The present invention allows the processing mode for write access operations to be set independently and respectively for prescribed units. The processing modes for handling write access are set previously for each of the volumes 6A and 6B. If the cache memory is functioning normally, write access operations to the ... 03/16/06 - 20060059316 - Method and apparatus for managing write back cache A network services processor includes an input/output bridge that avoids unnecessary updates to memory when cache blocks storing processed packet data are no longer required. The input/output bridge monitors requests to free buffers in memory received from cores and 10 units in the network services processor. Instead of writing the ... 03/16/06 - 20060059315 - Nonuniform chip multiprocessor In accordance with the present invention, an integrated circuit system and method are provided for increasing the number of processors on a single integrated circuit to a number that is larger than would typically be possible to coordinate on a single bus. In the present invention a two-level memory coherency ... 02/16/06 - 20060036813 - Method and device for distributing digital data in particular for a peer-to-peer network A method of transmitting digital images implemented in a server device able to cooperate with at least one client device connected to the server device through a telecommunication network, where the digital images comprising a plurality of elementary entities and the client device is able to request from the server ... 11/24/05 - 20050262310 - Methods and systems for halting synchronization loops in a distributed system The present provides for consistent resolution of data conflicts when synchronizing data between two or more devices in order to reduce the likelihood of an infinite synchronization loop within a distributed computing system. More particularly, example embodiments provide for a conflict resolution algorithm capable of generating unique values for properties ... 11/24/05 - 20050262309 - Proactive transfer ready resource management in storage area networks Systems and methods in accordance with various embodiments can manage transfer ready resources of one or more physical targets to avoid deadlock of a storage switch or storage area network when attempting to write data to a mirrored virtual target. When writing data to a mirrored virtual target, a storage ... 10/27/05 - 20050240734 - Cache coherence protocol A cache coherence protocol facilitates a distributed cache coherency conflict resolution in a multi-node system to resolve conflicts at a home node. ... 10/06/05 - 20050223176 - Sensory ego-sphere: a mediating interface between sensors and cognition A Sensory Ego-Sphere (SES) is an interface for a robot that serves to mediate information between sensors and cognition. The SES can be visualized as a sphere centered on the coordinate frame of the robot, spatially indexed by polar and azimuthal angles. Internally, the SES is a graph with a ... 09/29/05 - 20050216675 - Method and apparatus for directory-based coherence with distributed directory management The present invention provides for a type of parallel processing architecture in which a plurality of processors has access to a shared memory hierarchy level. A memory hierarchy level has a coherence directory and associated directory data with a plurality of cachelines each associated with different data. Buffers are interconnected ... 09/08/05 - 20050198441 - Multiprocessor system A shared memory multiprocessor is provided which includes a plurality of nodes connected to one another. Each node includes: a main memory for storing data; a cache memory for storing a copy of data obtained from the main memory; and a CPU for accessing the main memory and the cache ... 09/08/05 - 20050198440 - System and method to facilitate ordering point migration A system includes a first node that broadcasts a request for data. A second node having a first state associated with the data defines the second node as an ordering point for the data. The second node provides a response to the first node that transfers the ordering point to ... 07/21/05 - 20050160232 - System and method for conflict responses in a cache coherency protocol with ordering point migration Systems and methods are disclosed for interaction between different cache coherency protocols. One system may comprise a home node that receives a request for data from a first node in a first cache coherency protocol. A second node provides a conflict response to a request for the data from the ... 07/21/05 - 20050160231 - Cache coherency protocol with ordering points A system comprises a first node having an associated cache including data having an associated first cache state. The first cache state is capable of identifying the first node as being an ordering point for serializing requests from other nodes for the data. ... 07/21/05 - 20050160230 - System and method for responses between different cache coherency protocols Systems and method are disclosed for providing responses for different cache coherency protocols. One embodiment may comprise a system that includes a first node employing a first cache coherency protocol. A detector associated with the first node detects a condition based on responses provided by the first node to requests ... 06/30/05 - 20050144395 - Bandwidth-adaptive, hybrid, cache-coherence protocol A cache coordination mechanism for a multiprocessor, shared-memory computer switches between a snooping mechanism where an individual processor unit broadcasts or multicasts cache coherence messages to each other node on the system and a directory system where the individual processor unit transmits the cache control message to a directory which ... 06/23/05 - 20050138296 - Method and system to alter a cache policy Briefly, in accordance with an embodiment of the invention, a system and method to alter a cache policy of the system in response to the system transitioning from a first power state to a second power state is provided. The system may include a non-volatile disk cache and a disk ... 06/02/05 - 20050120182 - Method and apparatus for implementing cache coherence with adaptive write updates One embodiment of the present invention provides a system that facilitates cache coherence with adaptive write updates. During operation, a cache is initialized to operate using a write-invalidate protocol. During program execution, the system monitors the dynamic behavior of the cache. If the dynamic behavior indicates that better performance can ... ### FreshPatents.com Support |