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Electrical Computers And Digital Processing Systems: Memory > Storage Accessing And Control > Hierarchical Memories > Caching > Instruction Data Cache Instruction Data CacheInstruction Data Cache patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/21/06 - 20060212655 - Posted write buffers and method of posting write requests in memory modules A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first be coupled to the memory devices. The write request addresses are also posted in the buffer and compared ... 09/21/06 - 20060212654 - Method and apparatus for intelligent instruction caching using application characteristics A method and apparatus for intelligent instruction caching using application characteristics. In conjunction with building an application or application module, a function address map is generated identifying the location of functions to be cached in the application or module code. In conjunction with loading the application/module into system memory, a ... 09/07/06 - 20060200630 - Embedded system with instruction prefetching device, and method for fetching instructions in embedded systems In a method for fetching instructions in an embedded system, a predicted one of a set of the instructions stored in a memory device is fetched and is subsequently stored in an instruction buffer when a system bus is in a data access phase. When a processor generates an access ... 08/24/06 - 20060190686 - Cache circuit In the cache circuit, an instruction cache hit counter counts the number of cache hits, and an instruction memory access counter counts the number of times of instruction access. An instruction cache hit rate computation/entry disabling control circuit computes the ratio of the cache hit count to the instruction access ... 08/17/06 - 20060184738 - Unaligned memory access prediction In an instruction execution pipeline, the misalignment of memory access instructions is predicted. Based on the prediction, an additional micro-operation is generated in the pipeline prior to the effective address generation of the memory access instruction. The additional micro-operation accesses the memory falling across a predetermined address boundary. Predicting the ... 08/10/06 - 20060179226 - System and method of re-ordering store operations within a processor A system and method for re-ordering store operations from a processor core to a store queue. When a store queue receives a new processor-issued store operation from the processor core, a store queue controller allocates a new entry in the store queue. In response to allocating the new entry in ... 08/10/06 - 20060179225 - Reducing cache trashing of certain pieces Cache memory interrupt service routines (ISRs) influence the replacement of necessary instructions of the instruction stream (301) they interrupt; it is known as “instruction cache trashing,” since the instructions contained in the instruction cache (102) prior to execution of the ISR (302) are overwritten by the ISRs instructions. To reduce ... 08/03/06 - 20060174066 - Fractional-word writable architected register for direct accumulation of misaligned data One or more architected registers in a processor are fractional-word writable, and data from plural misaligned memory access operations are assembled directly in an architected register, without first assembling the data in a fractional-word writable, non-architected register and then transferring it to the architected register. In embodiments where a general-purpose ... 07/13/06 - 20060155932 - Method and apparatus for an efficient multi-path trace cache design A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced. ... 06/15/06 - 20060129764 - Methods and apparatus for storing a command In a first aspect, a first method is provided for storing a command. The first method includes the steps of (1) receiving a new command referencing an address; (2) determining whether the new command is dependent on at least one previously-received command referencing the address stored in a queue of ... 05/18/06 - 20060106987 - Load address dependency mechanism system and method in a high frequency, low power processor system The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a ... 05/18/06 - 20060106986 - System and method for managing data A system and method for managing data includes executing a set of instructions which are used for operating on compressed data and another set of instructions (e.g., different instructions) which are used for operating on uncompressed data. ... 05/18/06 - 20060106985 - Method and systems for executing load instructions that achieve sequential load consistency A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache ... 05/04/06 - 20060095674 - Tracing instruction flow in an integrated processor Tracing instruction flow in an integrated processor by defeaturing a cache hit into a cache miss to allow an instruction fetch to be made visible on a bus, which instruction would not have been made visible on the bus had the instruction fetch hit in the cache. The defeature activation ... 04/27/06 - 20060090035 - Method for priority scheduling and priority dispatching of store conditional operations in a store queue A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority ... 04/20/06 - 20060085599 - Processing of self-modifying code in multi-address-space and multi-processor systems A method and system of storing to an instruction stream with a multiprocessor or multiple-address-space system is disclosed. A central processing unit may cache instructions in a cache from a page of primary code stored in a memory storage unit. The central processing unit may execute cached instructions from the ... 03/30/06 - 20060069873 - Instruction cache using single-ported memories Systems, methodologies, media, and other embodiments associated with cache systems are described. One exemplary system embodiment includes an instruction cache comprising single-ported memories. The example system can further include a cache control logic configured to process cache events of different types that may be received by the instruction cache, and ... 02/16/06 - 20060036809 - Methods and apparatus for enforcing instruction-cache coherence Methods and apparatus for enforcing instruction-cache coherence are described herein. In an example method, a memory region of an instruction cache is initialized to form an initialized memory region prior to generating new code associated with the initialized memory region. Coherence code associated with the initialized memory region is generated. ... 12/08/05 - 20050273559 - Microprocessor architecture including unified cache debug unit A microprocessor architecture including a unified cache debug unit. A debug unit on the processor chip receives data/command signals from a unit of the execute stage of the multi-stage instruction pipeline of the processor and returns information to the execute stage unit. The cache debug unit is operatively connected to ... 12/01/05 - 20050268040 - Cache system having branch target address cache A cache system has a branch target address cache, including a storage unit for storing branch target address cache (BTAC) access bits each corresponding to cache lines of an instruction cache. The BTAC access bits represent a presence of a branch instruction on the next cache line of a cache ... 11/03/05 - 20050246498 - Instruction cache and method for reducing memory conflicts Read/write conflicts in an instruction cache memory (11) are reduced by configuring the memory as two even and odd array sub-blocks (12,13) and adding an input buffer (10) between the memory (11) and an update (16). Contentions between a memory read and a memory write are minimised by the buffer ... 10/06/05 - 20050223172 - Instruction-word addressable l0 instruction cache Methods and apparatuses associated with an L0 instruction cache. An L0 instruction cache stores sequences of instruction data and can be accessed in a single instruction clock cycle. In one embodiment pointers are used to define a window of valid instruction data. Instructions are stored in the cache sequentially, without ... 09/01/05 - 20050193175 - Low power semi-trace instruction cache A semi-trace cache combines elements and features of an instruction cache and a trace cache. An ICache portion of the semi-trace cache is filled with instructions fetched from the next level of the memory hierarchy while a TCache portion is filled with traces gleaned either from the actual stream of ... 06/09/05 - 20050125613 - Reconfigurable trace cache According to one embodiment a computer system is disclosed. The computer system includes a microprocessor and a chipset coupled to the microprocessor. The microprocessor removes stale branch instructions prior to the execution of a first cache line by finding existing branch prediction data for the first cache line. ... ### FreshPatents.com Support |