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Electrical Computers And Digital Processing Systems: Memory > Storage Accessing And Control > Hierarchical Memories > Caching > Multiple Caches > Hierarchical Caches Hierarchical CachesHierarchical Caches patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/21/06 - 20060212653 - Enhanced stcx design to improve subsequent load efficiency A method, system and computer program product for processing in a multiprocessor data processing system are disclosed. The method includes, in response to executing a load-and-reserve instruction in a processor core, the processing core sending a load-and-reserve operation for an address to a lower level cache of a memory hierarchy, ... 08/10/06 - 20060179223 - L2 cache array topology for large cache with different latency domains A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line over successive clock cycles. Larger wires ... 08/10/06 - 20060179222 - System bus structure for large l2 cache array topology with different latency domains A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data ... 07/27/06 - 20060168401 - Method and structure for high-performance linear algebra in the presence of limited outstanding miss slots A method and structure of increasing computational efficiency in a computer that comprises at least one processing unit, a first memory device servicing the at least one processing unit, and at least one other memory device servicing the at least one processing unit. The first memory device has a memory ... 06/22/06 - 20060136672 - Logging of level-two cache transactions into banks of the level-two cache for system rollback A plurality of processors on a chip is operated in lockstep. A crossbar switch on the chip couples and decouples the plurality of processors to a plurality of banks in a level-two (L2) cache. As data is stored in a first bank of the L2 cache, the old data at ... 06/22/06 - 20060136671 - Software controlled dynamic push cache Methods, software and systems of dynamically controlling push cache operations are presented. One method, which may also be implemented in software and/or hardware, monitors performance parameters and enables or disables push cache operations depending on whether the performance parameters are within a predetermined range. Another method, which may also be ... 05/11/06 - 20060101206 - Adaptive cache compression system Data in a cache is selectively compressed based on predictions as to whether the benefit of compression in reducing cache misses exceeds the cost of decompressing the compressed data. The prediction is based on an assessment of actual costs and benefits for previous instruction cycles of the same program providing ... 04/06/06 - 20060075193 - Methods and apparatus for controlling hierarchical cache memory Methods and apparatus for controlling hierarchical cache memories permit controlling a first level cache memory including a plurality of cache lines and controlling a next lower level cache memory including a plurality of cache lines. An additional memory may be associated with the next lower level cache memory and include ... 03/09/06 - 20060053255 - Apparatus and method for retrieving data from a data storage system In a memory controller such as a system controller including a level-3 cache memory for common use of data with a level-2 cache memory within a CPU by forming a chip set such as a server, an effective memory controller and a control method are realized to store the necessary ... 03/09/06 - 20060053254 - Data processing system and method for operating the same A data processing system according to the invention comprises a processor (P) and a memory hierarchy. The highest ranked level therein is a cache coupled to the processor. The memory hierarchy comprises a higher ranked cache (C1) having a cache controller (CC1) operating according to a write allocate scheme, and ... 02/09/06 - 20060031639 - Write unmodified data to controller read cache Disclosed are a method and apparatus, in a data storage environment with multiple devices sharing data, for writing data to one such device in a manner that indicates that the data need not be destaged to a lower tier of the storage hierarchy. As a specific example, a host computer ... 02/02/06 - 20060026355 - Cache memory and method for controlling cache memory A cache memory includes a first-level cache-memory unit that stores data; a second-level cache-memory unit that stores data that is same as the data stored in the first-level cache-memory unit; a storage unit that stores a part of information relating to the first-level cache-memory unit; and a coherence maintaining unit ... 01/26/06 - 20060020757 - Selectively performing fetches for store operations during speculative execution One embodiment of the present invention provides a processor which selectively fetches cache lines for store instructions during speculative-execution. During normal execution, the processor issues instructions for execution in program order. Upon encountering an instruction which generates a launch condition, the processor performs a checkpoint and begins the execution of ... 12/29/05 - 20050289299 - Digital data processing apparatus having multi-level register file A processor contains multiple levels of registers having different access latency. A relatively smaller set of registers is contained in a relatively faster higher level register bank, and a larger, more complete set of the registers is contained in a relatively slower lower level register bank. Physically, the higher level ... 12/29/05 - 20050289298 - Method and circuit to implement digital delay lines A delay line circuit and method to delay digital data in a main memory is provided. The delay line circuit may comprise primary delay line cache, secondary delay line cache, and a cache controller to control communication of data between the secondary delay cache and the primary delay cache. The ... 11/10/05 - 20050251624 - Method and apparatus for single instruction multiple data caching An apparatus and method for single instruction multiple data caching includes a memory access request generator operative to receive a primary access request. The method and apparatus further includes a cache controller coupled to the memory access request generator, wherein the cache controller is operative to execute a memory request. ... 08/25/05 - 20050188155 - High/low priority memory Methods and apparatus are provided for achieving low latency for high priority tasks in digital processing systems. A digital signal processor includes a core processor and a level one memory. In some embodiments, a store buffer is configured to hold write information for the level one memory and for a ... 08/04/05 - 20050172077 - Multi-level persisted template caching Methods and apparatuses are provided for use with a web server device, and which permit the web server logic to selectively store template data associated with one or more Active Server Pages (ASPs) or other like web pages in a multiple-level template storage arrangement that includes a first level storage ... 08/04/05 - 20050172076 - System for managing distributed cache resources on a computing grid A method and system of managing a cache is disclosed which comprises receiving a request for a resource, determining if a copy of the resource is stored in the cache, and the cache includes at least a first level of cache and a second level of cache. The method further ... 07/28/05 - 20050166019 - Multiple-level persisted template caching Methods and apparatuses are provided for use with a web server device, and which permit the web server logic to selectively store template data associated with one or more Active Server Pages (ASPs) or other like web pages in a multiple-level template storage arrangement that includes a first level storage ... 06/23/05 - 20050138292 - Provision of a victim cache within a storage cache heirarchy Apparatus, methods, and program products for storing data address a first cache and a second cache. The second cache is capable of operating in a first mode wherein data read for storage in the first cache is also stored in the second cache, and is capable of operating in a ... ### FreshPatents.com Support |