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Electrical Computers And Digital Processing Systems: Memory > Storage Accessing And Control > Hierarchical Memories > Caching > Multiple Caches Multiple CachesMultiple Caches patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/21/06 - 20060212652 - Information processing device and data control method in information processing device An information processing device of a multiprocessor configuration that can increase significantly the processing capability of read requests. The information processing device comprises a plurality of processing units, a plurality of cache memories for storing temporarily the data read by the plurality of processing units from respective main memories in ... 06/01/06 - 20060117142 - Disk array device, method for controlling the disk array device and storage system A disk array device is equipped with a plurality of input/output channels that receive data input/output requests from an external device, a plurality of cache memories provided for the corresponding respective input/output channels, each of the cache memories connected to each of the corresponding respective input/output channels, a disk drive ... 06/01/06 - 20060117141 - Parallel cachelets Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and apply each to a respective cachelet. Depending upon the content stored in each cachelet, the cachelet may generate ... 06/01/06 - 20060117140 - Memory control device and memory control method Address information of target data is stored in an ELA register at the start of a cache excluding process performed by BackEviction, and a request processing unit continuously re-executes a data acquiring process while an address of data requested to be acquired by a processor is present in the ELA ... 05/04/06 - 20060095673 - Mechanism for resolving ambiguous invalidates in a computer system The invention provides a system and method for resolving ambiguous invalidate messages received by an entity of a computer system. An invalidate message is considered ambiguous when the receiving entity cannot tell whether it applies to a previously victimized memory block or to a memory block that the entity is ... 04/13/06 - 20060080506 - Data replication in multiprocessor nuca systems to reduce horizontal cache thrashing A method of managing a distributed cache structure having separate cache banks, by detecting that a given cache line has been repeatedly accessed by two or more processors which share the cache, and replicating that cache line in at least two separate cache banks. The cache line is optimally replicated ... 03/02/06 - 20060047911 - Method and apparatus for enabling early memory reads for node local data A method, apparatus, and computer instructions for accessing data. In response to identifying a transaction requiring data, address information is obtained for the data. The address information includes an indication of whether the data is unlikely to be located on remote caches for local nodes. The remote caches for local ... 01/26/06 - 20060020756 - Contextual memory interface for network processor A memory subsystem includes multiple different caches configured for different types of data transfer operations between one or more processing units and a main memory. The different caches can include a first general cache configured for general random memory accesses, a software controlled cache used for controlling cache operations for ... 01/19/06 - 20060015686 - Cache memory management system and method A cache memory method and corresponding system for two-dimensional data processing, and in particular, two-dimensional image processing with simultaneous coordinate transformation is disclosed. The method uses a wide and fast primary cache memory (PCM) and a deep secondary cache memory (SCM), each with multiple banks to access data simultaneously. A ... 01/12/06 - 20060010293 - Cache for file system used in storage system A storage system and the cache device of the file system thereof are provided by the present invention. Each file system comprises at least one disk cache composed of a data cache unit used to temporarily store regular data and a plurality of dedicated cache units used to temporarily store ... 01/05/06 - 20060004961 - Direct processor cache access within a system having a coherent multi-processor protocol Methods and apparatuses for pushing data from a system agent to a cache memory. ... 12/01/05 - 20050268039 - Aggregate bandwidth through store miss management for cache-to-cache data transfer A method and system for reducing or avoiding store misses with a data cache block zero (DCBZ) instruction in cooperation with the underlying hardware load stream prefetching support for helping to increase effective aggregate bandwith. The method identifies and classifies unique streams in a loop based on dependency and reuse ... 11/24/05 - 20050262302 - Processing information received at an auxiliary computing device Described is a mechanism for receiving new data at an auxiliary device associated with a main computer system, and processing that new data within the auxiliary device firmware to take some action. The receipt and processing of the data is independent of whether the main computer system is in a ... 07/21/05 - 20050160225 - Self-tuning cache The present invention is a system, method and apparatus for self-tuning cache management. In a preferred aspect of the invention, a self-tuning cache can include a primary cache and at least two test caches. A first one of the test caches can have a cache size which is smaller than ... ### FreshPatents.com Support |