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Electrical Computers And Digital Processing Systems: Memory > Storage Accessing And Control > Hierarchical Memories > Caching CachingCaching patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236035 - Systems and methods for cpu repair In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is ... 10/19/06 - 20060236034 - External state cache for computer processor A processor can write its state to an external state cache. Thus, in the event of a processor failure, the stored state can be read and assumed, either by the original processor or another processor. Thus, a process can be resumed from the stored state rather than reconstructed from initial ... 10/19/06 - 20060236033 - System and method for the implementation of an adaptive cache policy in a storage controller A system and method for the implementation of an adaptive cache policy in a storage controller is disclosed in which a cache optimization utility monitors data access commands generated by one or more of the software applications of a server node. On the basis of one or more characteristics of ... 10/19/06 - 20060236032 - Data storage system having memory controller with embedded cpu A memory system includes a bank of memory, an interface to a packet switching network, and a memory controller. The memory system is adapted to receive by the interface a packet based command to access the bank of memory. The memory controller is adapted to execute initialization and configuration cycles ... 10/12/06 - 20060230232 - Attribute data management system Cache hit ratio is improved in a cache apparatus that reads and caches contents from a large-scale database. The cache apparatus includes a cache section for recording a plurality of sets. Each set includes an attribute ID, an extractor for extracting the attribute ID from an object ID, and attribute ... 10/12/06 - 20060230231 - Systems and methods for cpu repair In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is ... 10/12/06 - 20060230230 - Systems and methods for cpu repair In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is ... 10/12/06 - 20060230229 - Intelligent media caching based on device state A portable media device intelligently caches media based on device state. The portable media device has a hard disk memory to store the media (e.g., music, videos, movies, games, etc.) and a cache memory. When the device is in a state of user interaction (e.g., the user is navigating a ... 10/12/06 - 20060230228 - Determination of cache entry for future operation A system may include M cache entries, each of the M cache entries to transmit a signal indicating a read from or a write to the cache entry and comprising a data register and a memory address register, and K layers of decision cells, where K=log2M. The K layers M/2 ... 09/28/06 - 20060218349 - Device and method for caching control, and computer product A caching control device that controls caching of data stored in a storage device, includes a storing unit that stores information concerning memory allocated to the storage device as its cache memory, where the storing unit is installed in a first computer connected to a second computer via a network, ... 09/28/06 - 20060218348 - System and method for multiple cache-line size communications A system and method for facilitating communications between a plurality of devices that communicate using different cache-line sizes are disclosed. Briefly described, in architecture, one exemplary embodiment of a compatible cache-line communication system employs a plurality of first ports, each first port configured to receive communications from a first type ... 09/14/06 - 20060206669 - Efficient data storage system A system and method are disclosed for providing efficient data storage. A data stream comprising a plurality of data segments is received. The system determines whether one of the plurality of data segments has been stored previously using a summary in a low latency memory; in the event that the ... 09/14/06 - 20060206668 - Data processing system and data decompression method Compressed data is written from a main memory into a cache memory. The capacity of decompressed data corresponding to the compressed data is calculated. To ensure that cache mis does not occur upon subsequent data writing, an address of a location in which the decompressed data is to be stored ... 08/31/06 - 20060195660 - System and method for performing entity tag and cache control of a dynamically generated object not identified as cacheable in a network The present invention is directed towards a method and system for modifying by a cache responses from a server that do not identify a dynamically generated object as cacheable to identify the dynamically generated object to a client as cacheable in the response. In some embodiments, such as an embodiment ... 08/24/06 - 20060190685 - Method and apparatus for invalidating entries within a translation control entry (tce) cache A method and apparatus for invalidating entries within a translation control entry (TCE) cache are disclosed. A host bridge is coupled between a group of processors and a group of adaptors. The host bridge includes a TCE cache. The TCE cache contains the most-recently use copies of TCEs in a ... 08/17/06 - 20060184737 - Data stream generation method for enabling high-speed memory access An address processing section allocates addresses of desired data in a main memory, input from a control block, to any of three hit determination sections based on the type of the data. If the hit determination sections determine that the data stored in the allocated addresses does not exist in ... 08/17/06 - 20060184736 - Apparatus, system, and method for storing modified data An apparatus, system and method are disclosed for storing modified data. The apparatus includes a battery source for supplying backup power. The apparatus also includes a memory module for storing data. The memory module includes a backup portion and a non-backup portion. Only the backup portion is backed up by ... 08/17/06 - 20060184735 - Methodology for effectively utilizing processor cache in an electronic system A system and method for efficiently performing processing operations includes a processor configured to control processing operations in an electronic apparatus, and a memory coupled to the electronic apparatus for storing electronic information. A cache is provided for locally storing cache data copied by the processor from target data in ... 08/17/06 - 20060184734 - Method and apparatus for efficiently accessing both aligned and unaligned data from a memory A technique for improving access times when accessing memory, such as when accessing data from cache. By a unique manipulation and usage of a specified memory address in combination with the cache's internal organization, the address range required by the requested data can be covered by one odd and one ... 08/10/06 - 20060179221 - System and method for tracking changes in l1 data cache directory Method, system and computer program product for tracking changes in an L1 data cache directory. A method for tracking changes in an L1 data cache directory determines if data to be written to the L1 data cache is to be written to an address to be changed from an old ... 08/03/06 - 20060174064 - Method and arrangement for manipulation of the content of a data memory In a method and arrangement for manipulation of the contents of a data memory with which a processing device can be connected to manipulate (in at least one manipulation step at least one first memory range of the data memory, the processing device monitors a monitoring range of the first ... 08/03/06 - 20060174063 - Method of cooperative caching for distributed storage system An embodiment of a method of cooperative caching for a distributed storage system begins with a step of requesting data from storage devices which hold the data. The method continues with a step of receiving any cached blocks and expected response times for providing non-cached blocks from the storage devices. ... 08/03/06 - 20060174062 - Method and system for cache utilization by limiting number of pending cache line requests System and method for memory utilization in a computer system are described. In one embodiment, the method comprises, responsive to receipt of a new cache line-sized memory request, determining whether a number of pending requests is less than a fetch limit that is equal to or less than a number ... 07/27/06 - 20060168400 - Packet data placement in a processor cache Packet data received by a network controller is parsed and at least a portion of a received packet is stored by the network controller in both a host memory of a system and also in a cache memory of the central processing unit of the system. Other embodiments are described ... 07/27/06 - 20060168399 - Automatic generation of software-controlled caching and ordered synchronization A method for applying software controlled caching and ordered thread optimizations in network applications includes collecting statistics for program variables, selecting program variable candidates for ordered synchronization and/or software controlled cache optimization, performing a safety check to ensure candidates can be properly optimized, and generating code for selected optimization candidates. ... 07/20/06 - 20060161734 - Lazy flushing of translation lookaside buffers Address translation control (ATC) limits the mappings between virtual and physical addresses in order to implement a memory access policy. Each processor in a multi-processor system maintains a translation lookaside buffer (TLB) that caches mappings to speed translation of virtual addresses. Each processor also maintains a counter. Each time a ... 07/20/06 - 20060161733 - Host buffer queues The preferred embodiment of present invention is directed to an improved method and system for buffering incoming/unsolicited data received by a host computer that is connected to a network such as a storage area network. Specifically, in a host computer system in which the main memory of the host server ... 07/06/06 - 20060149902 - Apparatus and method for storing data in nonvolatile cache memory considering update ratio An apparatus and method for storing data in a nonvolatile cache memory considering an update ratio are provided. The apparatus includes a nonvolatile mass storage unit, a nonvolatile cache unit, and a memory controller for controlling the nonvolatile mass storage unit and the nonvolatile cache unit, and selectively storing the ... 06/29/06 - 20060143383 - Method, system and circuit for efficiently managing a cache storage device A system, method and circuit for efficiently managing a cache storage device. A cache storage device may include a cache management module. The cache management module may be adapted to generate a management unit and to associate the management unit with new data that is to be written into the ... 06/29/06 - 20060143382 - Reducing power consumption in a sequential cache In one embodiment, the present invention includes a cache memory, which may be a sequential cache, having multiple banks. Each of the banks includes a data array, a decoder coupled to the data array to select a set of the data array, and a sense amplifier. Only a bank to ... 06/22/06 - 20060136670 - Method and system for an atomically updated, central cache memory Disclosed is a central cache that is updated without the overhead of locking. Updates are “atomic” in that they cannot be interrupted part way through. Applications are always free to read data in the cache, accessing the data through a reference table. Applications do not directly update the cache, instead, ... 06/22/06 - 20060136669 - Cache refresh algorithm and method We present, in an exemplary embodiment of the present invention, a novel method for providing cache refresh within a finite time window (i.e., a time-box) with predictable accuracy and given constrained resources. Instead of refreshing the entire cache in a specified time window, we introduce an error. As used herein, ... 06/22/06 - 20060136668 - Allocating code objects between faster and slower memories Code objects stored in faster and slower memory may be checked to determine their access frequency. For example, in connection with a paging system, a reference count may be accessible. Based on the reference count and other statistics, code objects that are more frequently accessed may be moved to faster ... 06/22/06 - 20060136667 - System, method and program to preserve a cache of a virtual machine A system, computer program product and method for managing a cache of a virtual machine. A cache is defined in memory, and a virtual machine is assigned to the cache. An identity of the cache is recorded in storage. The virtual machine terminates, and the cache and contents of the ... 06/15/06 - 20060129763 - Virtual cache for disk cache insertion and eviction policies and recovery from device errors Processor-based systems may include a disk cache to increase system performance in a system that includes a processor and a disk drive. The disk cache may include physical cache lines and virtual cache lines to improve cache insertion and eviction policies. The virtual cache lines may also be useful when ... 06/15/06 - 20060129762 - Accessible buffer for use in parallel with a filling cacheline A cache system, used in conjunction with a processor of a computer system, is disclosed herein for increasing the processor access speed. The cache system comprising a cache controller in communication with the processor and cache memory in communication with the cache controller. The cache memory comprising a number of ... 06/08/06 - 20060123197 - System, method and computer program product for application-level cache-mapping awareness and reallocation The present invention provides an improved method, system, and computer program product that can optimize cache utilization. In one embodiment, a kernel service creates a storage map, and sending said storage map to an application. In one embodiment of the present invention, the step of the kernel service creating the ... 06/08/06 - 20060123196 - System, method and computer program product for application-level cache-mapping awareness and reallocation requests In view of the foregoing, the shortcomings of the prior art cache optimization techniques, the present invention provides an improved method, system, and computer program product that can optimize cache utilization. In one embodiment, an application requests a kernel cache map from a kernel service and the application receives the ... 06/08/06 - 20060123195 - Optionally pushing i/o data into a processor's cache Embodiments of the present invention are generally directed to a method, apparatus and system for a computing system implementing a technique known as cache push. The cache push technique enhances a single writer invalidation protocol with the ability to optionally push data into another processor's cache without changing the memory ... 06/08/06 - 20060123194 - Variable effective depth write buffer and methods thereof Data chunks are propagated through a write buffer from an input storage element to an output storage element by bypassing one or more intermediate storage elements of the write buffer. ... 06/01/06 - 20060117139 - Data-cache apparatus and a data-cache method used by a radio communications system A data-cache apparatus for providing a data-cache function to a radio communications system is disclosed. The data-cache apparatus includes a data distinguishing unit (310) to distinguish an attribute of data requested by a mobile station, a cache memory (340) that temporarily stores data provided to a mobile station, and a ... 05/18/06 - 20060106984 - Methods and apparatus for efficient memory usage In a first aspect, a first method is provided for efficient memory usage. The first method includes the steps of (1) determining whether data retrieved from a first storage device is characterized as data that is primarily read; and (2) if data retrieved from the first storage device is characterized ... 05/04/06 - 20060095672 - System and method for parallel execution of data generation tasks A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the ... 05/04/06 - 20060095671 - System, method and storage medium for providing data caching and data compression in a memory subsystem A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface ... 05/04/06 - 20060095670 - System, method and storage medium for providing an inter-integrated circuit (i2c) slave with read/write access to random access memory A method for data access via an inter-integrated circuit (I2C) protocol. The method includes receiving an I2C read command at an I2C slave device, where the I2C read command is from an I2C master device. The method also includes reading stored data from a storage device in response to receiving ... 05/04/06 - 20060095669 - Direct deposit using locking cache The present invention provides a method of storing data transferred from an I/O device, a network, or a disk into a portion of a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it ... 05/04/06 - 20060095668 - Method for processor to use locking cache as part of system memory The present invention provides a method for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache ... 04/27/06 - 20060090034 - System and method for providing a way memoization in a processing environment An apparatus is provided that a way memoization, which may utilize a memory address buffer element that is operable to store information associated with previously accessed addresses. The memory address buffer element may be accessed in order to reduce power consumption in accessing a cache memory. A plurality of entries ... 04/27/06 - 20060090033 - Facilitating server response optimization An algorithm facilitates optimization functionality for generating optimized response information. In facilitating such optimization, non-essential elements of the response information (i.e., unneeded for system interpretation) are eliminated thereby reducing the size of the response information and generating optimized response information as well as reducing the memory footprint of cache required ... 04/20/06 - 20060085598 - Storage-device resource allocation method and storage device Data writing into a storage device. Data is written into a cache memory in order to implement speeding-up, and also the data is written into a physical disc asynchronously therewith. Since allocation of the cache memory is performed on each writing-request basis, a cut-out processing is required which is executed ... 04/20/06 - 20060085597 - On-demand cache memory for storage subsystems A cache on-demand module employing a cache performance module for managing size adjustments to an active cache size of a cache memory in view of supporting an optimal performance of a storage subsystem employing the cache memory by determining an optimal active cache size of the cache memory for supporting ... 04/06/06 - 20060075192 - Dynamic reconfiguration of cache memory In one embodiment, a processing node includes a plurality of processor cores each including a cache memory coupled to a cache monitor unit and to a configuration unit. Each cache monitor unit may be configured to independently monitor a current utilization of the cache memory to which it is coupled ... 03/30/06 - 20060069871 - System and method for dynamic sizing of cache sequential list A self-tuning, low overhead, simple to implement, locally adaptive, novel cache management policy that dynamically and adaptively partitions the cache space amongst sequential and random streams so as to reduce read misses. ... 03/30/06 - 20060069870 - Method and system for improved reliability in storage devices A method of preventing data loss in a data storage system includes supplying write data to a high speed volatile write buffer and supplying electrical power from an energy storage device upon detection of a primary power loss event. The backup electrical power is supplied to the write buffer and ... 03/30/06 - 20060069869 - Enqueueing entries in a packet queue referencing packets Provided are a method, system, network processor, network device, and article of manufacture for enqueueing entries in a packet queue referencing packets. When adding a packet to a first memory area, an entry is written to a packet queue in a second memory area referencing the added packet. A pointer ... 03/16/06 - 20060059309 - Cache memory system and control method of the cache memory system To improve the efficiency of access to a system memory associated with changes (writes) to cache data, a cache line having the same memory size as write data is selected and the write data is written into the selected cache line, thereby reducing the number of accesses to the system ... 03/09/06 - 20060053253 - Caching control for streaming media Improved caching control for streaming media includes one or more cache control directives associated with streaming media content that can be used by a source of the streaming media content to identify how caching proxy servers are to handle the streaming media content. Upon receipt of the streaming media content, ... 02/16/06 - 20060036807 - System controller, speculative fetching method, and information processing apparatus A system controller, which executes a speculative fetch from a memory before determining whether data requested for a memory fetch request is in a cache by searching tag information of the cache, includes a consumption determining unit that monitors a consumption status of a hardware resource used in the speculative ... 02/02/06 - 20060026354 - Cache memory usable as scratch pad storage A processor adapted to couple to external memory. The processor comprises a controller and data storage. The data storage is usable to store local variables and temporary data and is configurable to operate in either a cache policy mode in which a miss results in an access of the external ... 02/02/06 - 20060026353 - Memory usable in cache mode or scratch pad mode to reduce the frequency of memory accesses A processor adapted to couple to external memory. The processor comprises a controller and data storage (e.g., cache memory). The data storage is configurable to operate in either a cache policy mode in which a miss results in an access of the external memory or in a scratch pad policy ... 02/02/06 - 20060026352 - Second-cache driving/controlling circuit, second cache, ram, and second-cache driving/controlling method A circuit for driving and controlling a second cache that is incorporated in a processor and comprises a plurality of RAM. The circuit comprises a second-cache control unit 1A and a chip-enable control unit 61. The second-cache control unit 1A receives an access request for an access to the second ... 01/19/06 - 20060015685 - Cache controller, cache control method, and controller Disclosed is a controller which includes a CPU, a cache control unit, a tag control unit, a data unit, and a ROM. The cache control unit executes cache control operations for a process executed on the CPU, based on the process identifier in one of cache access modes: (A) cache ... 01/12/06 - 20060010292 - Multi-purpose register cache A technique to use available register cache resources if register file resources are unavailable. Embodiments of the invention pertain to a register cache writeback algorithm for storing writeback data to a register cache if register file write ports or space is unavailable. ... 01/05/06 - 20060004960 - Faster method of erasing flash memory An erase operation in a flash memory device includes applying an erase pulse to memory cells of the flash memory device to convert the contents of the memory cells into logic 1 bits before any pre-programming operation is performed. ... 01/05/06 - 20060004959 - System and method for heterogeneous caching The caching of heterogeneous bean sets has been improved from requiring each bean to have its own cache instance to caching the beans in a single cache. The beans can be identified by generating a unique identifier that is a combination of the bean's primary key and a self-reference identifier ... 12/29/05 - 20050289297 - Processor and semiconductor device A processor that includes reconfigurable processing circits for performing predetermined processing, in which a compiler is made capable of determining storage of configuration data in a cache. Configuration data for defining a configuration of the processing circuit contains cache operation information defining an operation of a cache. A cache operation ... 12/22/05 - 20050283572 - Semiconductor integrated circuit and power-saving control method thereof A semiconductor integrated circuit has an SDRAM and a group of elements, whose power consumption is controlled (referred to as “power-controlled block”). The power-controlled block includes a CPU and a memory control circuit. A power control circuit outputs a power-down signal to an output-fixing circuit when a power-saving mode setting ... 12/01/05 - 20050268038 - Methods and apparatus for providing a software implemented cache memory Methods and apparatus provide a processor for operative connection to a main memory for storing data, the processor being operable to request at least some of the data for use; and a local memory in operative connection with the processor such that the data may be stored therein for use ... 12/01/05 - 20050268037 - Cache hit ratio estimating apparatus, cache hit ratio estimating method, program, and recording medium Determining a cache hit ratio of a caching device analytically and precisely. There is provided a cache hit ratio estimating apparatus for estimating the cache hit ratio of a caching device, caching access target data accessed by a requesting device, including: an access request arrival frequency obtaining section for obtaining ... 11/24/05 - 20050262301 - Method and apparatus for delaying interfering accesses from other threads during transactional program execution One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional execution. During transactional execution of a block of instructions, the system receives a request from another thread (or processor) to perform a memory access involving a cache line. If performing ... 11/17/05 - 20050257008 - Program conversion apparatus and processor A program conversion apparatus converts an input program into a program operable by a processor using a cache memory and outputs the converted program. The program conversion apparatus includes a target region extraction section for extracting from regions of a memory, as a target region, a region in which writing ... 11/17/05 - 20050257007 - Remote access method for accessing dynacache data A method for accessing an internal dynamic cache of a Websphere-type Application Server (WAS) from an external component that includes the step of establishing a software interface component within the WAS. The software interface component can receive a request from the external component. The request can include an identifier for ... 11/17/05 - 20050257006 - Device linkage control apparatus A device linkage control system for controlling a plurality of devices in linkage with each other to suit the life pattern of a user, by extracting life pattern information of a user from an operating history of the plurality of devices, comprising: a life data recording apparatus (n107) for accumulating, ... 11/10/05 - 20050251623 - Method for completing full cacheline stores with address-only bus operations A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a ... 11/10/05 - 20050251622 - Method to stall store operations to increase chances of gathering full entries for updating cachelines A method and processor system that substantially enhances the store gathering capabilities of a store queue entry to enable gathering of a maximum number of proximate-in-time store operations before the entry is selected for dispatch. A counter is provided for each entry to track a time since a last gather ... 11/10/05 - 20050251621 - Method for realizing autonomous load/store by using symbolic machine code The invention describes a method for realizing autonomous load/store by using symbolic machine code. Instructions in symbolic machine code may have operands and/or results specifying symbolic variables. Symbolic variables naturally arise as the machine code pendant of pointer variables declared in a program written in some high level programming language. ... 11/03/05 - 20050246497 - Method and apparatus for accelerating retrieval of data from a memory system with cache by reducing latency A memory controller controls a buffer which stores the most recently used addresses and associated data, but the data stored in the buffer is only a portion of a row of data (termed row head data) stored in main memory. In a memory access initiated by the CPU, both the ... 10/27/05 - 20050240730 - Analyzing, indexing and seeking of streaming information A streaming information handling system receives streaming information and analyzes the streaming information to locate one or more sync points in the streaming information. The streaming information and sync point location information, indicative of a location of the sync points, is provided to a storage module. The streaming information and ... 10/27/05 - 20050240729 - Access to a wide memory A processing system includes a processor and a physical memory (500) with a single-size memory port (505) for accessing data in the memory. The processor is arranged to operate on data of at least a first data size and a smaller second data size. The first data size is equal ... 10/20/05 - 20050235114 - System and method for adaptively managing pages in a memory An adaptive replacement cache policy dynamically maintains two lists of pages, a recency list and a frequency list, in addition to a cache directory. The policy keeps these two lists to roughly the same size, the cache size c. Together, the two lists remember twice the number of pages that ... 10/20/05 - 20050235113 - System for storing streaming information in a circular buffer by using padding block containing non-streaming information to fill a partition of the buffer One aspect of the present invention relates to an information appliance for handling streaming information for storage in a circular buffer having a plurality of partitions defined by boundaries. The information appliance includes receiving streaming information from a source of streaming information and forming data blocks wherein each data block ... 10/20/05 - 20050235112 - Method and system for handling streaming information One aspect of the present invention leads to a method of handling streaming information. The method includes receiving the streaming information and analyzing the streaming information to locate one or more points of interest in the streaming information. An index of the one or more points of interest are generated. ... 10/20/05 - 20050235111 - Methods for operating a cpu having an internal data cache A CPU 3 having a processor 1 and an internal data cache 7 IS operated in combination with a dummy interface 13 which simulates the existence of an external memory 17 having the same address space as the cache memory 7 but which does not store data written to it. ... 10/13/05 - 20050228951 - Virtualized load buffers A memory addressing technique using load buffers-to improve data access performance. More particularly, embodiments of the invention relate to a method and apparatus to improve cache access performance in a computer system by exploiting addressing mode information within an instruction accessing a cache memory or other memory device within the ... 09/29/05 - 20050216670 - Method and system for caching presentation data A method and system for retrieving and maintaining presentation data in a presentation cache is provided. In a preferred embodiment, a presentation cache object provides a presentation cache with multiple cache entries. Each entry contains an indication of the format of the presentation data and the presentation data stored in ... 09/29/05 - 20050216669 - Efficient data storage system A method for storing data comprising is disclosed. The method comprises receiving a data stream comprising a plurality of data segments wherein each data segment is associated with an identifier. The method further determining using a subset of identifiers that are stored in a low latency memory whether a data ... 09/29/05 - 20050216668 - Mode device, administrative server, routing method and authentication method A diskless computer is allowed to finish a write request with no influence of a storage device and a network of the storage device. A node device 104 passes on information sent and received between a diskless computer 101 and a storage device 102. When information sent from the diskless ... 09/29/05 - 20050216667 - Method of implementing off-chip cache memory in dual-use sram memory for network processors A method, apparatus, and system for implementing off-chip cache memory in dual-use static random access memory (SRAM) memory for network processors. An off-chip SRAM memory store is partitioned into a resizable cache region and general-purpose use region (i.e., conventional SRAM use). The cache region is used to store cached data ... 09/29/05 - 20050216666 - Cached memory system and cache controller for embedded digital signal processor A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory ... 09/22/05 - 20050210197 - Cache mechanism According to one embodiment a system is disclosed. The system includes a central processing unit (CPU), a first cache memory coupled to the CPU to store only data for vital loads that are to be immediately processed at the CPU, a second cache memory coupled to the CPU to store ... 09/08/05 - 20050198437 - Method and system for coalescing coherence messages The ability to combine a plurality of remote read miss requests and/or a plurality of exclusive access requests into a single network packet for efficiently utilizing network bandwidth. This combination exists for a plurality of processors in a network configuration. In contrast, other solutions have inefficiently utilized network bandwidth by ... 09/01/05 - 20050193174 - System bus read data transfers with data ordering control bits A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to effectuate data transfer, determining at the system component logic the order in which to transmit data ... 09/01/05 - 20050193173 - Methodology, system, and computer-readable medium for collecting data from a computer A computerized method for collecting suspected data of interest from a computer comprises searching the computer's shot-term memory to locate at least one target memory range containing the suspected data of interest, and copying the suspected data of interest within the target memory range to an alternate data storage location ... 09/01/05 - 20050193172 - Method and apparatus for splitting a cache operation into multiple phases and multiple clock domains A method and apparatus for splitting a cache operation into multiple phases and multiple clock domains are disclosed. The method according to the present techniques comprises splitting a cache operation into two or more phases and two or more clock domains. ... 09/01/05 - 20050193171 - Computer system cache controller and methods of operation of a cache controller In at least some embodiments, a computer system comprises a central processing unit (“CPU”), a bridge device coupled to a main memory, and a cache controller coupled between the bridge device and the CPU. The computer system further comprises a cache memory coupled to the cache controller and providing memory ... 08/25/05 - 20050188154 - Cache memory with reduced power and increased memory bandwidth A digital processor with a cache that provides fast and low power operation. The cache contains a tag array and a data array. The tag array indicates whether a value is stored in the cache for a particular external address. Access to the data array is necessary to determine the ... 08/18/05 - 20050182902 - Signal processing apparatus A signal processing apparatus (1) performs decoding using a first memory area (11) of a main memory (10), a first table (13) of a second memory area (12) and a second table (14). The signal processing apparatus (1) has a cache memory (34) for temporarily storing data of the first ... 08/11/05 - 20050177687 - Storage system including hierarchical cache metadata A storage system including hierarchical cache metadata storages includes a cache, a first metadata storage, and a second metadata storage. In one embodiment, the cache may store a plurality of data blocks in a first plurality of locations. The first metadata storage may include a plurality of entries that stores ... 07/21/05 - 20050160224 - Context-sensitive caching A method of caching contextually variant objects in a common cache. The method can include identifying an object type for a requested object and determining whether the requested object has an object type which is specified among an enumerated set of cacheable object types which can be stored in the ... 07/07/05 - 20050149681 - Predictive filtering of register cache entry A mechanism, which supports predictive register cache allocation and entry, uses a counter look-up table to determine the potential significances of physical register references. ... 07/07/05 - 20050149680 - Fast associativity collision array and cascaded priority select Embodiments of the present invention provide a fast associativity collision array and cascaded priority select. An instruction fetch unit may receive an instruction and may search a primary data array and a collision data array for requested data. The instruction fetch unit may forward the requested data to a next ... 06/30/05 - 20050144388 - Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information A memory controller is described that comprises a compression map cache. The compression map cache is to store information that identifies a cache line's worth of information that has been compressed with another cache line's worth of information. A processor and a memory controller integrated on a same semiconductor die ... 06/30/05 - 20050144387 - Mechanism to include hints within compressed data According to one embodiment a computer system is disclosed. The computer system includes a central processing unit (CPU), a cache memory coupled to the CPU and a cache controller coupled to the cache memory. The cache memory includes a plurality of compressible cache lines to store additional data. The cache ... 06/30/05 - 20050144386 - Mechanism to store reordered data with compression According to one embodiment a computer system is disclosed. The computer system includes a central processing unit (CPU), a cache memory coupled to the CPU and a cache controller, coupled to the cache memory. The cache memory includes a plurality of compressible cache lines to store additional data. The cache ... 06/23/05 - 20050138291 - System and method for caching results In certain aspects, the invention features a system and method for caching results, including receiving a job for computation by a distributed computing system having one or more node computing devices in communication with a cache, processing, on one of the node computing devices, the job to create an intermediate ... 06/23/05 - 20050138290 - System and method for instruction rescheduling Embodiments of the present invention relate to selectively re-executing instructions in a computer processor based on their association with a particular cache miss. ... 06/23/05 - 20050138289 - Virtual cache for disk cache insertion and eviction policies and recovery from device errors Processor-based systems may include a disk cache to increase system performance in a system that includes a processor and a disk drive. The disk cache may include physical cache lines and virtual cache lines to improve cache insertion and eviction policies. The virtual cache lines may also be useful when ... 06/16/05 - 20050132138 - Memory cache bank prediction A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, ... 06/02/05 - 20050120178 - Organization of cache memory for hardware acceleration of the finite-difference time-domain method Disclosed herein is an organization of cache memory for hardware acceleration of the FDTD method. The organization of cache memory for hardware acceleration of the FDTD method provides a substantial speedup to the finite-difference time-domain (FDTD) algorithm when implemented in a piece of digital hardware. The organization of cache memory ... ### FreshPatents.com Support |