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Electrical Computers And Digital Processing Systems: Memory > Storage Accessing And Control > Specific Memory Composition > Solid-state Random Access Memory (ram) > Dynamic Random Access Memory > Refresh Scheduling Refresh SchedulingRefresh Scheduling patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236027 - Variable memory array self-refresh rates in suspend and standby modes Self-refresh rates of a memory unit may be managed based on temperature. In one embodiment of the invention, the invention may include measuring the temperature of a memory unit, the memory unit having a self-refresh rate to maintain data integrity, comparing the measured temperature to a threshold, and adjusting the ... 08/24/06 - 20060190678 - Static random access memory (sram) compatible, high availability memory array and method employing synchronous dynamic random access memory (dram) in conjunction with a single dram cache and tag A static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tag provides a memory architecture comprising low cost DRAM memory cells that is available for system accesses 100% of the time and ... 06/29/06 - 20060143372 - Directed auto-refresh synchronization In a directed auto-refresh (DARF) mode, refresh commands are issued by a controller, and refresh row and bank addresses are maintained internally to a memory module. A bank address counter internal to the memory is initialized to a first predetermined value upon entering DARF mode. The memory refreshes the currently ... 06/29/06 - 20060143371 - Integrated memory management apparatus, systems, and methods Apparatus and systems, as well as methods and articles, may perform operations including memory bank management and memory bus arbitration associated with a first memory module comprising non-refreshable memory cells and a controller, a second memory module coupled to the first memory module by a memory management control bus, or ... 06/15/06 - 20060129756 - Computer arrangement using non-refreshed dram A computer arrangement with a processor (5) and at least one memory unit (7, 9, 11, 13) connected to the processor (5) and including dynamic random access memory (13), wherein the computer arrangment is arranged to use but not to refresh at least part of the dynamic random access memory ... 06/08/06 - 20060123188 - Semiconductor device and electronic instrument A semiconductor device including: a DRAM which is a volatile memory; a PLL circuit which outputs an operation clock signal generated by multiplying an input clock signal; a circuit block which operates in synchronization with the operation clock signal; first and second refresh controllers for requesting a refresh operation of ... 05/25/06 - 20060112217 - Method and system for minimizing impact of refresh operations on volatile memory performance A memory system is provided. The system includes a volatile memory, a refresh counter configured to monitor a number of advanced refreshes performed in the volatile memory, and a controller configured to check the refresh counter to determine whether a regularly scheduled refresh can be skipped in response to detecting ... 03/30/06 - 20060069856 - Memory controller method and system compensating for memory cell data losses A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from ... 03/30/06 - 20060069855 - System and method for controlling the access and refresh of a memory The present invention provides a memory and memory control system wherein, except for one case noted below, the main memory gives priority to read or write operations over refresh operations. On the other hand, the cache memory give priority to the refresh operations over read or write operations. The exceptional ... 03/02/06 - 20060047893 - Non-skipping auto-refresh in a dram In a dynamic random access memory device, an auto-refresh method comprises receiving a command for the memory device to operate in a half-density mode. This causes a remapping circuit to remap a first memory address bit to an unused memory address location. Using the new addressing scheme, an auto-refresh operation ... 01/05/06 - 20060004955 - Dynamic memory supporting simultaneous refresh and data-access transactions Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to ... 01/05/06 - 20060004954 - System and method for refreshing random access memory cells A method for operating a memory device that comprises periodically generating a refresh request signal for performing a refresh operation, providing an access request signal for performing an access operation, performing the refresh operation if the refresh request signal occurs prior to the access request signal, and performing the access ... 12/29/05 - 20050289294 - Dram with half and full density operation Methods and apparatus for operating a memory in a half density or a full density mode, and switching between the modes when required. A memory device defaults to half density operation upon startup for lower power consumption, and seitches to full density operation when the lower addresses are full. When ... 12/29/05 - 20050289293 - Dual-port dram cell with simultaneous access A dual-port memory substantially eliminates noise problems associated with the staggered methods of operation. The first and second word lines of a dual-port memory cell are simultaneously activated, such that all four bit lines associated with the cell also move at the same time. The dual-port memory uses simple control ... 12/22/05 - 20050283567 - Persistent, real-time determination of the freshness of changeable data associated with a container The invention efficiently determines whether a container that is associated with an item of changeable data actually is associated with the freshest version of this item of changeable data. Multiple containers may exist in the virtual memory (“in-memory container”) or in a persistent storage system (“persistent container”) of a computer ... 10/20/05 - 20050235102 - Memory controller, semiconductor integrated circuit device, microcomputer, and electronic equipment An auto refresh control circuit of a memory controller comprises an auto refresh request generation circuit that generates auto refresh requests at the predetermined intervals, a hold count circuit that holds an auto refresh request to the dynamic random access memory in the state of being impossible to access a ... 10/20/05 - 20050235101 - Memory controller, semiconductor integrated circuit device, semiconductor device, microcomputer, and electronic device A memory controller is connected with a first memory requiring refresh and a second memory not requiring refresh, both of which share part of a bus, comprising: a first memory controller that conducts access control and auto-refresh control for the first memory; a second memory controller that conducts access control ... 10/20/05 - 20050235100 - Semiconductor integrated circuit device, microcomputer, and electronic equipment A semiconductor integrated circuit device includes a memory controller which performs access control based on an access request from the host with respect to a dynamic random access memory having a self-refresh function. The memory controller includes a counter which counts a specified period after detecting an idle state, as ... 09/22/05 - 20050210186 - Semiconductor device A semiconductor device able to improve data retaining characteristics and decrease power consumption, further able to realize more unrestricted system without increasing excessive circuits, and having the following: an ALPG receiving a start signal and a mode selection signal to generate commands and addresses with respect to a DRAM circuit ... 07/28/05 - 20050166009 - Integrated circuit random access memory capable of automatic internal refresh of memory array A dynamic random access memory integrated circuit and method includes internal refresh control and an array configured to receive read and write access requests having priority over pending refresh requests, wherein refresh requests are queueable and retired on clock cycles not requiring an access of the array and complete in ... 06/09/05 - 20050125597 - Compensated refresh oscillator A method and apparatus is provided for implementing a refresh rate control scheme that is capable of compensating for external factors. Using a circuit, a change in a current leakage relating to at least a portion of a memory device is detected. Furthermore, a refresh rate associated with the portion ... ### FreshPatents.com Support |