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Electrical Computers And Digital Processing Systems: Memory > Storage Accessing And Control > Specific Memory Composition > Solid-state Random Access Memory (ram) > Dynamic Random Access Memory Dynamic Random Access MemoryDynamic Random Access Memory patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.08/24/06 - 20060190677 - Sequential nibble burst ordering for data A combination of circuits for use in a memory device is comprised of a decode circuit responsive to a first portion of address information for identifying a word to be read or written. The decode circuit is further responsive to a second portion of the address information for identifying an ... 08/24/06 - 20060190676 - Static random access memory (sram) compatible, high availability memory array and method employing synchronous dynamic random access memory (dram) in conjunction with a data cache and separate read and write registers and tag blocks A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to ... 08/17/06 - 20060184726 - Flexible access and control of dynamic random access memory The invention relates in general to a method for accessing data stored in a dynamic random access memory. To enable flexible use of different types of memory modules, the invention provides addressing data through at least one address bus, controlling at least data flow to and from the dynamic random ... 08/10/06 - 20060179213 - Executing background writes to idle dimms Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to ... 06/22/06 - 20060136658 - Ddr2 sdram memory module A DDR2 SDRAM memory module having memory chips arranged bilaterally symmetrical on the module. A register chip is arranged on each of two faces of the memory module, with each register chip coupled to half of the memory chips. ... 06/15/06 - 20060129755 - Memory rank decoder for a multi-rank dual inline memory module (dimm) The invention refers to a Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module (DIMM) having a predetermined number of DRAM memory chips mounted on a printer circuit board (PCB), wherein each DRAM memory chip comprises a predetermined number of stacked DRAM memory dies which are selectable by a ... 06/15/06 - 20060129754 - Reuse of functional data buffers for pattern buffers in xdr dram A method, an apparatus, and a computer program are provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for ... 05/25/06 - 20060112216 - Methods and structures for efficient storage of task file information in serial ata environments Methods and structures for efficiently storing task file information for a significant number of SATA devices coupled to a SATA storage controller. A RAM memory within the SATA storage controller may store task file information for virtually any number of SATA devices coupled to a SAS communication domain. An arbiter ... 05/18/06 - 20060106975 - Structure of sequencers that perform initial and periodic calibrations in an xdrtm memory system A structure of sequencers, a method, and a computer program are provided for performing initial and periodic calibrations in an XDR™ memory system. A memory controller that performs these calibrations is divided into identical, independent halves, with each half containing a Current/Impedance Calibration (i/z Cal) sequencer and six Bank sequencers. ... 05/18/06 - 20060106974 - Dynamic random access memory controller and video system A dynamic random access memory controller is suitable in controlling a first dynamic random access memory and a second dynamic random access memory, which two memory capacities are not the same. The judging circuit of the dynamic random access memory controller receives and judges whether or not a system addressing ... 05/04/06 - 20060095652 - Memory device and method for receiving instruction data Memory device and method for receiving instruction data. One embodiment provides a memory device including a memory array, an instruction unit for receiving an instruction data and for performing a memory related operation depending on the instruction data, address and command inputs for receiving a set of instruction signals, a ... 03/30/06 - 20060069854 - Method and apparatus providing efficient queue descriptor memory access A system having queue control structures includes a conflict avoidance mechanism to prevent memory bank conflicts for queue descriptor access. In one embodiment, a queue descriptor bank table contains information including in which memory bank each queue descriptor is stored. ... 03/23/06 - 20060064540 - Continuous interleave burst access A system is described which uses a burst access memory and a memory controller to anticipate the memory address to be used in future data read operations as requested by a microprocessor. Either the memory controller or the memory device initiates a burst read operation starting at a memory address ... 03/16/06 - 20060059299 - Apparatus and method for pipelined memory operations A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle ... 03/16/06 - 20060059298 - Memory module with memory devices of different capacity A memory module includes a first set of at least one first type of memory device and a second set of at least one second type of memory device having a higher capacity than the first type. In addition, an additional capacity portion of the first and second sets stores ... 03/09/06 - 20060053248 - Techniques for implementing accurate operating current values stored in a database Memory modules and methods for fabricating and implementing memory modules wherein unique operating current values corresponding to specific memory devices on the memory modules are accessed from a database such that the operating current values may be implemented to improve system performance. Memory modules comprising a number of volatile memory ... 03/02/06 - 20060047892 - Method for resolving parameters of dram A method for resolving DRAM parameters includes setting a chip number, a DIMM number and a DRAM bank number of the DRAM according to the chip number, the DIMM number and the DRAM bank number recorded on a SPD of the DRAM. The method further includes initializing the DRAM with ... 03/02/06 - 20060047891 - System and method for transmitting data packets in a computer system having a memory hub architecture A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled ... 03/02/06 - 20060047890 - Sdram address mapping optimized for two-dimensional access Typically, a bulk of the memory space utilized by an SOC (103) is located in cheaper off-chip memory devices such as Synchronous Dynamic Random Access Memory (SDRAM) memories (104). These memories provide a large capacity for data storage, at a relatively low cost. It is common for SOC devices to ... 02/23/06 - 20060041714 - Method for controlling memories of a plurality of kinds and circuit for controlling memories of a plurality of kinds It is made possible to control RAMs of a plurality of kinds differing in control system by using a single memory controller (LSI). A memory control circuit having an LSI configuration receives a RAM access request signal, which does not depend on a classification of a RAM device, from a ... 02/23/06 - 20060041713 - Method and system for reducing pin count in an integrated circuit when interfacing to a memory The invention provides a system and method for reducing pin count in an integrated circuit (IC) when interfacing to a synchronous dynamic random access memory (SDRAM). The SDRAM has a plurality of address lines and a plurality of data lines. The method includes connecting together the plurality of data lines ... 02/09/06 - 20060031628 - Buffer management in a network device without sram A technique for performing buffer management on a network device without using static random access memory (SRAM). In one embodiment, a software-based buffer management scheme is used to allocate metadata buffers and packet buffers in one or more dynamic random access memory (DRAM) stores. As metadata buffers are allocated, pointers ... 02/02/06 - 20060026342 - Dram access command queuing structure Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing ... 01/05/06 - 20060004953 - Method and apparatus for increased memory bandwidth Memory apparatus and methods for increased memory bandwidth. A memory agent may receive data on an inbound, northbound or memory link. A memory agent may utilize extra write bandwidth on an otherwise underutilized port or link. Other embodiments are described and claimed. ... 12/29/05 - 20050289292 - System and method for thermal throttling of memory modules Some embodiments of the invention accurately account for power dissipation in memory systems that include individual memory modules by keeping track of the number of read requests, the number of write requests, and the number of activate requests that are applied to the individual memory modules during selected time periods. ... 12/01/05 - 20050268027 - Data processor The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a ... 11/03/05 - 20050246481 - Memory controller with command queue look-ahead In general, in one aspect, the disclosure describes accessing multiple memory access commands from a one of multiple memory access command queues associated with, respective, banks of a Random Access Memory (RAM) and selecting one of the commands based, at least in part, on the memory access operations identified by ... 10/20/05 - 20050235099 - Memory device interface An interface device provided on a motherboard, or with a memory control chip set, translates between a controller, intended to communicate with a packet based memory system, and a non-packet based memory system. Communications from a memory controller, intended to directly communicate with a RAMBUS RDRAM memory system, are translated ... 10/13/05 - 20050228939 - System and method for optimizing interconnections of components in a multichip memory module An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are arranged around the hub in pairs, ... 10/06/05 - 20050223161 - Memory hub and access method having internal row caching A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The memory hub includes a row cache memory that stores data as they are read from the memory devices. When the memory module is ... 10/06/05 - 20050223160 - Memory controller A memory controller which can freely set parameters without a significant increase in circuit scale. Selection information and addition information applied from a CPU as a data signal are held in a register. The selection information is commonly applied to a plurality of selectors as a selection signal, while the ... 09/29/05 - 20050216654 - System and module including a memory device having a power down mode A memory module comprises a memory device including a memory array to store data. An interface receives an instruction to exit a power down mode. A register stores a value representative of a period of time to elapse between exiting from the power down mode and a time at which ... 09/22/05 - 20050210185 - System and method for organizing data transfers with memory hub memory modules A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hubs each include a transmit interface having a data organization system that organizes a command header and data for each of a plurality of memory transactions ... 09/15/05 - 20050204094 - Memory post-write page closing apparatus and method Apparatus and method to receive new requests for write transactions; compare rank, bank and page of new requests to those already stored and assemble chains of write commands directed to the same rank, bank and page; select and transmit write commands from one chain at a time until each chain ... 09/15/05 - 20050204093 - Memory post-write page closing apparatus and method Apparatus and method to select write transactions and to selectively mark a write transaction with a page closing hint to cause the page in a memory device to which the write transaction is directed to be closed immediately after the write transaction is carried out if no other write transaction ... 09/01/05 - 20050193163 - Integrated circuit buffer device An integrated circuit buffer device comprises a first receiver circuit to receive control information and address information from a controller device. A first interface includes a first interface portion to provide a first address to a first memory device. A second interface portion provides a first control signal to the ... 08/25/05 - 20050188150 - Method and apparatus for providing a memory with write enable information A method is described for providing a memory with a serial sequence of write enable signals that are offset in time with respect to respective data received by a plurality of data inputs of the memory. A memory is also described with an array for data storage, a plurality of ... 08/18/05 - 20050182894 - Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (sso) on memory bus timing A method and system transfer read data from a memory device having a data bus and a data masking pin adapted to receive a masking signal during write operations of the memory device. The method includes placing a sequence of read data words on the data bus and applying a ... 07/28/05 - 20050166008 - Semiconductor memory device and circuit arrangement The invention provides a semiconductor memory device that includes at least two memory banks. The semiconductor memory device is designed in such a way that: at least two processor units can carry out read accesses and write accesses to memory banks; and by means of an inhibit command communicated by ... 07/28/05 - 20050166007 - Information processing apparatus and method of accessing memory The present invention makes it possible to inexpensively and quickly execute a process of rewriting data stored in a memory, thus reducing the power consumption of an information processing apparatus. In connection with a conventional Read-Modify-Write function, an information processing apparatus 1 first issues a write instruction, and after all ... 07/28/05 - 20050166006 - System including a host connected serially in a chain to one or more memory modules that include a cache A system including a host coupled to a serially connected chain of memory modules. In one embodiment, at least one of the memory modules includes a cache for storing data stored in a system memory. ... 07/14/05 - 20050154820 - Memory controller connection to ram using buffer interface A memory subsystem controller and buffer for a computer and a second buffer for memory tag operations. The buffers are linked to the memory controller by two bidirectional data busses. The controller operates the memory subsystem by passing memory addresses to the memory subsystem data bus through the buffers. Unidirectional ... 07/07/05 - 20050149665 - Scratchpad memory An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM. ... 06/30/05 - 20050144375 - Method and apparatus to counter mismatched burst lengths Memory device having banks of memory cells organized into two groups of banks that share control circuitry and a data buffer to provide an interface to a memory bus, but which are independently operable enough to support unrelated transactions with each group, and can be used to stagger read operations ... 06/30/05 - 20050144374 - Hardware detected command-per-clock A memory controller is coupled to a memory device via a memory channel. The memory controller includes a command-per-clock detection unit that compares a portion of a current address with a portion of a previous address. If there is a match, then the memory controller can continue to assert a ... 06/30/05 - 20050144373 - System and method for variable array architecture for memories A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is disclosed. An exemplary embodiment includes a memory system containing a plurality of arrays, each in communication with a common controller, wherein the arrays are activated ... 06/30/05 - 20050144372 - Memory device controlled with user-defined commands A memory device controllable with user-defined commands includes a memory array accessible for reading and writing data therein, a command module that receives user-defined commands for controlling access to the memory array, and a mode module that stores command definitions respectively associated with the user-defined commands. Each command definition includes ... 06/30/05 - 20050144371 - Burst mode implementation in a memory device A memory device, such as a DRAM, includes a memory array that is accessible for writing data in and reading data out, and a command decoder that decodes input control signals to produce commands for accessing the memory array. The set of commands for controlling access to the memory device ... 06/30/05 - 20050144370 - Synchronous dynamic random access memory interface and method A memory interface allows access SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n(n>1) column memory addresses from the received column address. The interface accesses the ... 06/30/05 - 20050144369 - Address space, bus system, memory controller and device system Memory capacity requirements in systems-on-chip have led to the use of DRAM-based memory devices. A property of these devices is the burst-oriented access of data. These bursts can be considered as successive non-overlapping blocks of data in the memory that can only be accessed as an entity. Therefore, when a ... 06/23/05 - 20050138277 - Data control circuit for ddr sdram controller A data control circuit for a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) that secures a stable reading/writing operation of DDR SDRAM data by generating an actively controllable internal data strobe signal. The data control circuit includes an internal data strobe signal generating circuit generating and outputting an ... 06/23/05 - 20050138276 - Methods and apparatus for high bandwidth random access using dynamic random access memory The inventive subject matter provides various apparatus and methods to perform high-speed memory read accesses on dynamic random access memories (“DRAMs”) for read-intensive memory applications. In an embodiment, at least one input/output (“I/O”) channel of a memory controller is coupled to a pair of DRAM chips via a common address/control ... 06/16/05 - 20050132131 - Partial bank dram precharge A “partial PRECHARGE command” is used to precharge a fraction of the banks in a multi-bank DRAM. In a first implementation the command precharges one half of the banks. In a second implementation the command precharges one quarter of the banks. The power drawn by the upper or lower bank ... 06/09/05 - 20050125596 - Access control unit and method for use with synchronous dynamic random access memory device An access control unit and method is proposed for use with an SDRAM (Synchronous Dynamic Random-Access Memory) device to control each round of burst-transfer type of access operation on the SDRAM device. The proposed access control unit and method is characterized by that the column-address strobe signal involved in each ... ### FreshPatents.com Support |