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Electrical Computers And Digital Processing Systems: Memory > Addressing Combined With Specific Memory Configuration Or System > For Multiple Memory Modules (e.g., Banks, Interleaved Memory) For Multiple Memory Modules (e.g., Banks, Interleaved Memory)For Multiple Memory Modules (e.g., Banks, Interleaved Memory) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236021 - Method for addressing a symbol in a memory and device for processing symbols A bitwise addressing mode includes including the shaping of symbols of variable length during an operation for reading or writing a symbol in a bank of memories. The addressing is then done with the aid of a word address and of a bit pointer designating the start of the symbol ... 10/05/06 - 20060224814 - Semiconductor memory devices having controllable input/output bit architectures and related methods A semiconductor memory device may include a semiconductor substrate, a first unit memory device on the substrate, and a second unit memory device on the substrate. The first unit memory device may be configured to receive first through Nth data bits and/or to provide first through Nth data bits to ... 09/21/06 - 20060212643 - Methods and apparatus for dynamic linking program overlay Methods and apparatus provide for loading at least one software program module from a storage medium into a local memory of a processor for execution, the storage medium containing a main module and a plurality of sub-modules of the software program; and updating an address table, copies of the address ... 08/24/06 - 20060190671 - Memory device and method having multiple internal data buses and memory bank interleaving A memory device and method receives write data through a unidirectional downstream bus and outputs read data through a unidirectional upstream bus. The downstream bus is coupled to a pair of internal write data buses, and the upstream bus is coupled to a pair of internal read data buses. A ... 08/24/06 - 20060190670 - Semiconductor memory device, controller, and read/write control method thereof A controller 102 and four flash memories F0 to F3 are connected by twos to two memory buses, and each flash memory is divided into two regions of substantially the same size to form a first half and a last half regions. In a four-memory configuration, a consecutive logical address ... 08/10/06 - 20060179206 - Programmable bank/timer address folding in memory devices A set of N copies of bank control logic are provided for tracking the banks within the memory modules (DRAMS). When the total number of banks within the memory module(s) is greater than N, the addresses of particular banks are folded into a single grouping. The banks are represented by ... 08/10/06 - 20060179205 - [expandable integrated circuit and operation procedure thereof] An expandable integrated circuit (IC) and an operation procedure thereof are provided. The expandable IC comprises the CPU and a RAM for writing data or program for correction into the CPU so that the manufacturer need not replace the ROM when the data or program in IC needs to be ... 07/27/06 - 20060168390 - Methods and apparatus for dynamically managing banked memory Techniques for controllably allocating a portion of a plurality of memory banks as cache memory are disclosed. To this end, a configuration tracker and a bank selector are employed. The configuration tracker configures whether each memory bank is to operate in a cache or not. The bank selector has a ... 07/13/06 - 20060155911 - Extended register microprocessor An extended register processor includes a register file having a legacy register set and an extended register set. The extended register set includes a plurality of extended registers accessible only to extended register instructions. The processor maps extended register references to physical extended registers at run time. The processor includes ... 07/13/06 - 20060155910 - Sonet data byte switch A switch system including a plurality of input ports and a plurality of output ports for transferring data from one of the input ports to one of the output ports, and a plurality of memory devices is disclosed. The memory devices include a first memory bank configured for data being ... 06/22/06 - 20060136652 - Electronic system with remap function and method for generating bank with remap function An electronic system with remap function comprises a memory unit, a remap unit, and a microprocessor. The memory unit at least has a first bank and a second bank, which have a common area and a non-common area, respectively. The common area of the first bank comprises an addressing table ... 06/15/06 - 20060129742 - Direct-memory access for content addressable memory A network device for processing packets. The network device includes a CPU processing module for transmitting information between at least one memory location on the network device and an external CPU memory location. The CPU processing module includes a first engine for performing bulk transfer of information from the at ... 06/15/06 - 20060129741 - Method and apparatus for accessing memory in a computer system architecture supporting heterogeneous configurations of memory structures A computer system includes at least one processor, multiple memory modules embodying a main memory, a communications medium for communicating data between the at least one processor and main memory, and memory access control logic which controls the routing of data and access to memory. The communications medium and memory ... 06/15/06 - 20060129740 - Memory device, memory controller and method for operating the same One embodiment of the present invention provides a memory device comprising a plurality of sets of memory banks, wherein each memory bank includes a memory array and is adapted to be read out in a data access; a plurality of internal data buses and a plurality of internal command and ... 06/15/06 - 20060129739 - Method controller having tables mapping memory addresses to memory modules A memory controller includes ports and corresponding tables. Each port is receptive to one or more memory modules. Each table includes entries mapping memory addresses to the memory modules. Each entry corresponds to no more than one of the memory modules. The tables support asymmetric population of the memory modules ... 03/23/06 - 20060064535 - Efficient multi-bank memory queuing system Systems and techniques for queuing commands in a multi-banked memory is disclosed. The systems and techniques include storing and retrieving data from a memory over a bus. The memory may include a plurality of memory banks. In at least one embodiment of a system or technique to queue commands, a ... 03/02/06 - 20060047886 - Memory controller A memory controller maps a processor generated address to a banked DRAM address by applying a randomising function which results in the banks appearing in an irregular and non-cyclic order in the conceptual memory map. Incremental addressing by two or more requestors is thereby more evenly distributed amongst the banks ... 03/02/06 - 20060047885 - Configurable memory module and method for configuring the same A configurable memory module capable of multiple times of use is provided. A string of register bits is used to mark a usage status of the memory segments. The register bits are converted into a sequence of segment identification bits as the most significant bits of a sequence of memory ... 01/26/06 - 20060020739 - Burst counter controller and method in a memory device operable in a 2-bit prefetch mode A burst counter generates all but the least significant bit (“LSB”) of a sequence of column addresses in a 2-bit prefetch dynamic random access memory (“DRAM”). The sequence of column addresses is generated by either incrementing or decrementing the burst counter starting from an externally applied starting address. The count ... 01/05/06 - 20060004943 - Computer system for interleave memory accessing among a plurality of nodes Destination registers are provided in a chipset and node information is set in the destination registers. The destination address is selected in accordance with a physical address to be accessed to thereby decided a node provided with a memory to be accessed. The magnitude of the load of the memory ... 12/15/05 - 20050278474 - Method of increasing ddr memory bandwidth in ddr sdram modules The present invention provides a method of increasing DDR memory bandwidth in DDR SDRAM modules. DDR memory has an inherent feature called the Variable Early Read command, where the read command is issued one CAS latency before the termination of an ongoing data burst By using the Variable Early Read ... 12/01/05 - 20050268024 - Memory controller for use in multi-thread pipeline bus system and memory control method In a memory control method in a multiple-thread pipeline system, addresses of a plurality of banks to be accessed in a memory unit are received in sequence from a master. For each of the plurality of banks, it is determined whether an address that corresponds to the bank is input ... 12/01/05 - 20050268023 - Multi-port random access memory A memory system is presented. The memory system includes a plurality of memory banks, a plurality of busses and a selection mechanism. The selection mechanism is connected to every memory bank in the plurality of memory banks and to every bus in the plurality of busses. The selection mechanism is ... 12/01/05 - 20050268022 - Cache line memory and method therefor A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of ... 11/24/05 - 20050262288 - Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be directly stored in either a normal mode or vertical mode in the memory is disclosed. A connection circuit is provided ... 11/24/05 - 20050262287 - Dynamic memory reconfiguration for signal processing A system and method for processing data (e.g., encoded audio data in an audio decoder). Various aspects of the present invention may comprise a first memory module comprising a first software module and a second software module. A signal-processing module may comprise a processor and local memory. A first data ... 11/17/05 - 20050256996 - Register read circuit using the remainders of modulo of a register number by the number of register sub-banks A register read circuit reads out register values of X (natural number) registers corresponding to selection register numbers. The registers are each assigned to a unique register number. Register numbers that correspond to the X registers to be selected among the registers are given to the register read circuit as ... 11/10/05 - 20050251615 - Microcomputer A single chip type microcomputer includes at least a central processing unit (CPU), a random-access memory (RAM), a mask read-only memory (CPU) and an electrically writable ROM such as an electrically erasable and programmable read-only memory (EEPROM). The electrically writable ROM stores both the user program and data to be ... 11/10/05 - 20050251614 - Processer The present invention provides a processor including: a plurality of memory banks; a read-address generation circuit for supplying a read address to each of the memory banks on the basis of a read-register specification and a read-register scan direction; a read control circuit for executing control to rearrange a plurality ... 10/27/05 - 20050240717 - Interleaved mapping method of block-index-to-sdram-address for optical storage (cd/dvd) system A method for storing data into a SRDAM. The method comprises the following steps: receiving a plurality of blocks of data; labeling said blocks successively from 1 in step of 1; dividing the label of each of said blocks by M and acquiring a corresponding remainder for each of said ... 10/06/05 - 20050223155 - Memory configuration apparatus, systems, and methods An apparatus and a system, as well as a method and article, may operate to control a bandwidth of a memory coupled to a plurality of data processing units responsive to protocol indications, such as a number of data processing units in use. In some embodiments, apparatus and systems, as ... 08/25/05 - 20050188146 - Fifo module, deskew circuit and rate matching circuit having the same A first-in-first-out (FIFO) module is disclosed. The FIFO module includes multiple individually addressable memory locations, a write pointer, a read pointer and at least additional pointer. The write pointer is connected to the memory bank for addressing a first memory location to write a datum on an input data bus ... 08/11/05 - 20050177675 - Deferred tuple space programming of expansion modules The present invention permits deferring the final provisioning of the Card Information Structure (CIS) in the attribute memory space of expansion cards (or modules) for portable hosts. This enables expansion cards to be distributed, sold, and installed by their end-users prior to the final provisioning, which is performed during their ... 08/11/05 - 20050177674 - Configurable embedded processor A microprocessor system includes a multi-bank memory having a first memory bank and a second memory bank, a muxing circuit, a CPU and a DMA controller. The muxing circuit allows the CPU to access one of the memory bank while allowing the DMA controller access to the other memory bank ... 07/21/05 - 20050160216 - Memory system and method for assigning addresses to memory devices A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each ... 07/07/05 - 20050149662 - System having a plurality of integrated circuit buffer devices A system comprises a master device and a first integrated circuit buffer device. A first plurality of integrated circuit memory devices are coupled to the first integrated circuit buffer device. A first plurality of signal lines are coupled to the first integrated circuit buffer device and the master device, wherein ... 06/09/05 - 20050125594 - Memory with synchronous bank architecture In a synchronous multi-port bank memory, registers/buffers receive a read/write signal and an address signal from each of external ports, receive and send a data signal to and from each of the external ports, and receive and send a port block signal. An access conflict management circuit receives the address ... ### FreshPatents.com Support |