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Electrical Computers And Digital Processing Systems: Memory > Addressing Combined With Specific Memory Configuration Or System > Addressing Cache Memories Addressing Cache MemoriesAddressing Cache Memories patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236020 - Cache memory architecture and associated microprocessor and system controller designs A single memory element, which may consist of general purpose SRAM chips, implements both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purpose RAM used by a microprocessor as an external cache ... 10/12/06 - 20060230221 - Mobile electronic device and data process system utilizing the same A memory system includes a processor providing a data access address; a set of control registers storing memory configuration information; a memory device comprising a first predetermined number of ways, the processor selectively configuring a selected number less than or equal to the first predetermined number of the ways as ... 09/07/06 - 20060200615 - Systems and methods for adaptively mapping an instruction cache Systems and methods for adaptively mapping system memory address bits into an instruction tag and an index into the cache are disclosed. More particularly, hardware and software are disclosed for observing collisions that occur for a given mapping of system memory bits into a tag and an index. Based on ... 06/15/06 - 20060129738 - Data allocation in a distributed storage system A method for data distribution, including distributing logical addresses among an initial set of devices so as provide balanced access, and transferring the data to the devices in accordance with the logical addresses. If a device is added to the initial set, forming an extended set, the logical addresses are ... 06/15/06 - 20060129737 - Data allocation in a distributed storage system A method for data distribution, including distributing logical addresses among an initial set of devices so as provide balanced access, and transferring the data to the devices in accordance with the logical addresses. If a device is added to the initial set, forming an extended set, the logical addresses are ... 06/01/06 - 20060117129 - High speed dram cache architecture A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memory page containing data for a plurality ... 03/30/06 - 20060069843 - Apparatus and method for filtering unused sub-blocks in cache memories A memory system and method includes a cache having a filtered portion and an unfiltered portion. The filtered portion is divided into block sized components, and the unfiltered portion is divided into sub-block sized components. Blocks evicted from the filtered portion have selected sub-blocks thereof cached in the unfiltered portion ... 03/09/06 - 20060053245 - Power reduction for processor front-end by caching decoded instructions A power aware front-end unit for a processor may include a UOP cache that disables other circuitry within the front-end unit. In an embodiment, a front-end unit may disable instruction synchronization circuitry, instruction decode circuitry and, optionally, instruction fetch circuitry while instruction look-ups are underway in both a block cache ... 03/02/06 - 20060047884 - System and method for power efficent memory caching A system and method for power efficient memory caching. Some illustrative embodiments may include a system comprising: a hash address generator coupled to an address bus (the hash address generator converts a bus address present on the address bus into a current hashed address); a cache memory coupled to the ... 03/02/06 - 20060047883 - Serially indexing a cache memory In one embodiment, the present invention includes a method of accessing a cache memory to determine whether requested data is present. In this embodiment, the method may include indexing a cache with a first index corresponding to a first memory region size, and indexing the cache with a second index ... 01/05/06 - 20060004942 - Multiple-core processor with support for multiple virtual processors A multiple-core processor with support for multiple virtual processors. In one embodiment, a processor may include a cache including a number of cache banks, a number of processor cores and core/bank mapping logic coupled to the cache banks and processor cores. During a first mode of processor operation, each of ... 01/05/06 - 20060004941 - Method, system, and program for accessesing a virtualized data structure table in cache Provided are a method, system, and program for caching a virtualized data structure table. In one embodiment, an input/output (I/O) device has a cache subsystem for a data structure table which has been virtualized. As a consequence, the data structure table cache may be addressed using a virtual address or ... 12/08/05 - 20050273545 - Flexible techniques for associating cache memories with processors and main memory Caches are associated with processors, such multiple caches may be associated with multiple processors. This association may be different for different main memory address ranges. The techniques of the invention are flexible, as a system designer can choose how the caches are associated with processors and main memory banks, and ... 12/01/05 - 20050268021 - Method and system for operating a cache memory Method and system for operating a cache memory. The method includes the steps of splitting the cache memory into sets, addressing the cache memory using a processor address which is split into at least two fields, and forming one of the fields of the processor address for addressing the cache ... 10/27/05 - 20050240716 - System and method for interfacing index based and interator based application programming interfaces A system and method for interfacing index based and iterator based file management routines. In general, the disclosed system maintains an iterator cache having multiple iterators. Each active iterator is associated with a most recently used directory entry. Upon receiving an index based request, the iterator closest to the index ... 10/27/05 - 20050240715 - K-way direct mapped cache A method and apparatus for a k-way direct mapped cache organization is herein described. Control logic coupled to a cache may associate an address to a way within a plurality based on a first portion of the address. The control logic may match the first portion of the address to ... 10/06/05 - 20050223153 - Physically-tagged cache with virtual fill buffers A virtually indexed, physically-tagged cache is combined with one or more virtually-tagged fill-buffers. ... 09/22/05 - 20050210179 - Integrated circuit having random clock or random delay An integrated circuit comprising: at least one active device that outputs light during a change in state of the at least one device during operation; a clock circuit configured to output a clock signal to the at least one active device, the clock signal rate being varied so as to ... 09/01/05 - 20050193160 - Database system providing methodology for extended memory support A database system providing methodology for extended memory support is described. In one embodiment, for example, a method is described for extended memory support in a database system having a primary cache, the method comprises steps of: creating a secondary cache in memory available to the database system; mapping a ... 08/11/05 - 20050177673 - Fast unaligned cache access system and method A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the cache lines are split among the towers, unaligned cache access ... 08/11/05 - 20050177672 - Storage system structure for storing relational cache metadata A storage system includes a cache and a collection of metadata, organized by their associations with regard to the data they represent. In one embodiment, the cache stores data blocks in a first plurality of locations. A first metadata storage stores metadata including block addresses of data blocks within the ... 06/23/05 - 20050138264 - Cache memory A cache memory is configured by a CAM, comprising a CAM unit for storing a head pointer indicating the head address of a data block being stored, the pointer map memory for storing a series of connecting relationships between pointers indicating addresses of data constituting a block and starting from ... 06/09/05 - 20050125592 - Multi-level cache having overlapping congruence groups of associativity sets in different cache levels A computer cache memory having at least two levels includes associativity sets allocated to congruence groups, each congruence group having multiple associativity sets (preferably two) in the higher level cache and multiple associativity sets (preferably three) in the lower level cache. The address range of an associativity set in the ... ### FreshPatents.com Support |