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Electrical Computers And Digital Processing Systems: Memory > Addressing Combined With Specific Memory Configuration Or System Addressing Combined With Specific Memory Configuration Or SystemAddressing Combined With Specific Memory Configuration Or System patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236019 - Libraries and data structures of materials removed by debulking catheters Material removed by a debulking catheter from a body lumen can be preserved. Materials can be collected from many different patients and/or from multiple procedures on individual patients. Data which describe the properties or qualities of the removed material and/or the patient and/or the patient's family or environment can be ... 07/13/06 - 20060155909 - Methods relating to configuration of software A method relating to configuration of software includes receiving a request sent from a sender computer system to a recipient computer system. The sender computer system including software that has an unsuccessful configuration. The sender computer system is requesting the recipient computer system to provide a new configuration for the ... 06/08/06 - 20060123183 - System and method for viewing digital visual content on a device A system and method for viewing material displayed on an electronic device. When a user desires to view a document, only a portion of which is viewable on a display at a given moment, the portion is displayed on the display as a primary image. A secondary image is then ... 05/18/06 - 20060106969 - Memory controller and method for writing to a memory The invention provides a controller for a memory having at least one memory cell, that involves a higher cost for writing than for reading. The memory cell is allocated to a first address information and adapted to store memory data. The memory controller of the invention comprises a register. A ... 04/06/06 - 20060075180 - Methods and apparatuses for automated circuit design Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a logic function feeding a carry chain is implemented through extending the carry chain and through using the extended portion of the carry chain. In one aspect of an embodiment, control/non-control loads are separated from each other ... 02/02/06 - 20060026335 - Method and apparatus for provisioning a communications client on a host device An apparatus for provisioning a data communications client on a host communications device, the host communications device adapted to operate on a communications network, the apparatus comprising: a first data store adapted to store variant configuration information; a second data store adapted to store provisioning information; a provisioning module adapted ... 01/26/06 - 20060020738 - Method and apparatus for supporting shared library text replication across a fork system call A fork system call by a first process is detected. A second process is created as a replication of the first process with a second affinity. If a replication of the replicated shared library is present in the second affinity domain, effective addresses of the replication of the replicated shared ... 01/05/06 - 20060004940 - Operation apparatus, operation apparatus control method, program and computer readable information recording medium An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such ... 12/29/05 - 20050289287 - Method and apparatus for interfacing between test system and embedded memory on test mode setting operation A method of entering memory module mounted on a memory system or a plurality of memories mounted on the memory module into a test mode, and a first register and a second register for performing the method are introduced. Each of the memory manufacturers provides a different MRS code for ... 12/29/05 - 20050289286 - Multi-core processor control method The load/sense control of the setting value that corresponds to the processor core for CMP, etc. processors that have multi-cores realize, for such processors with multi-core structures, the shortening of system boot time during multi-core operation, flexible debugging methods, and improvement of yield with the aid of partial core quality ... 12/29/05 - 20050289285 - Method and apparatus for loading relocatable in-place executable files in a virtual machine One embodiment of the present invention provides a system that facilitates loading of an in-place executable file into a virtual machine. The system operates by loading the in-place executable file into the virtual machine, where the in-place executable file contains internal pointers that point to memory locations within the in-place ... 12/29/05 - 20050289284 - High speed memory modules Apparatus and method for producing memory modules having a plurality of branches connected to a memory bus, each branch containing at least one dynamic random access memory (DRAM) device or synchronous random access memory (SDRAM) device connected to the memory bus via at least one transmission signal (TS) line and/or ... 12/29/05 - 20050289283 - Autonomic computing utilizing a sequestered processing resource on a host cpu An autonomic computing environment is provided by sequestering one of a plurality of processor resources, partitioning a memory, and hiding an input/output (I/O) device. One processor resource is sequestered such that the sequestered processor resource is not exposed to the remaining processor resources as a processor resource. A memory region ... 12/29/05 - 20050289282 - Device, system and method of memory mapping Briefly, some embodiments of the invention may provide devices, systems and methods of memory mapping for one or more virtual machines. For example, a method in accordance with an embodiment of the invention may include mapping a memory area as a first category in relation to a first address space ... 12/15/05 - 20050278473 - Method and apparatus for processing data in a processing unit being a thread in a multithreading environment A method and an apparatus for creating a data block (Error Correction Code Block) comprising a plurality of data sectors, which data block is provided with parity information, and a method and an apparatus for recovering data sectors from a data block provided with parity information. A method for encoding ... 11/24/05 - 20050262286 - Intelligent memory device multilevel ascii interpreter System and method for interpreting ASCII code fetched from a code space of a task partition that is part of memory shared by a host processor and a multitask controller (MTC). The MTC includes a scheduler unit, a data flow unit, an executive unit, and a resource manager unit. The ... 11/17/05 - 20050256995 - Preserving memory resources by liimiting time-date information for a subset of properties Example embodiments provide for preserving memory resources by selecting property values to be assigned time-date information used in resolving conflicts between sync values. The property values may be selected based on the available resources of a remote device, e.g., when the time-date information is to be stored in a field ... 11/10/05 - 20050251613 - Synchronized storage providing multiple synchronization semantics A shared resource access control system having a gating storage responsive to a plurality of controls with each of the controls derived from an instruction context identifying the shared resource, the gating storage including a plurality of sets of access method functions with each set of access method functions including ... 10/27/05 - 20050240714 - System and method for virtual content repository deployment A system and method for manipulating a virtual content repository (VCR) containing information, comprising, integrating a plurality of repositories into the VCR, creating an external representation of the information, wherein the external representation preserves hierarchical relationships of the information, wherein the information is organized as a hierarchical namespace that encompasses ... 10/20/05 - 20050235094 - Information processor capable of using past processing space An information processor uses the past processing space to shorten the time spent for starting up programs, thereby increasing convenience for the user. A memory unit provides memory space that can be used as processing space. A control unit retains, in the memory space of the memory unit, the processing ... 10/20/05 - 20050235093 - Apparatus and method for managing registers in a processor to emulate a portion of stack The present invention is generally directed to method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage a plurality of processor registers to store the top portion of the stack. Data is managed in these registers by managing a pointer that points to a ... 10/13/05 - 20050228936 - Method and apparatus for managing context switches using a context switch history table A method, apparatus and computer instructions for storing data relating to the switch in a context switch history containing a number of prior context switches occurring prior to a current context. The storing of data occurs in response to a change in context for a direct memory access resource. Portions ... 09/22/05 - 20050210178 - Intelligent memory device with variable size task architecture A variable task size architecture is disclosed. A system partition is included that is dedicated to system use. The system partition contains a number of specifiers that describe the number of tasks in the system memory, and for each task partition, the location and size of a task status register, ... 08/18/05 - 20050182888 - Disk array apparatus and disk array apparatus control method A journal write unit writes journal data into a third storage device. The journal data includes an identifier of a logical volume in a first storage device into which data has been written, information of a location in which the data is stored in the logical volume, update time which ... 08/11/05 - 20050177671 - Intelligent memory device clock distribution architecture A computing system that includes one or more processing elements, a memory connected to a host processor and a multitask controller, where the multitask controller includes a scheduler unit, a data flow unit, an executive unit, and a resource manager unit. The processing elements, the scheduler unit, the data flow ... 07/28/05 - 20050165999 - Memory device having strobe terminals with multiple functions A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device and transfer output data from the memory device. The write strobe transceivers transfer timing information of the input data. The read strobe transceivers transfer timing information of ... 07/21/05 - 20050160215 - Flow through asynchronous elastic fifo apparatus and method for implementing multi-engine parsing and authentication A flow through asynchronous elastic first-in, first-out (FIFO) apparatus and method are provided for implementing multi-engine parsing and authentication. A FIFO random access memory (RAM) has a data input for receiving data and control information and a data output for outputting the data and control information. The FIFO RAM includes ... 07/07/05 - 20050149661 - Reduction of noise and temperature variation in mixed-signal integrated circuits The present method reduces variations in noise and temperature in a mixed-signal circuit including memory. Memory electrically proximate an analog circuit is provided and a digital data word received at the memory. When the data word is not a desired data word, a dummy write to the memory is performed. ... 06/23/05 - 20050138263 - Method and apparatus to retain system control when a buffer overflow attack occurs A function call is executed during execution of a program. In response, a return address of the call is saved in a first stack and in a second stack, allocated by the operating system. After the called function is executed, the return addresses stored in the first and second stack ... 06/23/05 - 20050138262 - Flash memory having a high-permittivity tunnel dielectric A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages. The flash memory cell has a substrate with source/drain regions. The high-k tunneling dielectric is formed above the substrate. The high-k tunneling dielectric can be ... 06/16/05 - 20050132119 - Current mode logic scheme and circuit for matchline sense amplifier design using constant current bias cascode current mirrors A CAM device features matchlines which are coupled in series between a top current source, a bottom current source, and ground. The top current source is configured to supply a first current to the matchline and the bottom current source, while the bottom current source is configured to supply a ... 06/09/05 - 20050125591 - Semiconductor memory device having hierarchical bit line structure A semiconductor memory device comprising: a memory array including a plurality of memory cells; a plurality of word lines corresponding to the respective memory cells; a pair of local bit lines corresponding to the memory array; a pair of global bit lines corresponding to the pair of local bit lines; ... 06/02/05 - 20050120160 - System and method for managing virtual servers A management capability is provided for a virtual computing platform. In one example, this platform allows interconnected physical resources such as processors, memory, network interfaces and storage interfaces to be abstracted and mapped to virtual resources (e.g., virtual mainframes, virtual partitions). Virtual resources contained in a virtual partition can be ... 06/02/05 - 20050120159 - Integrated memory device with multiple reading and writing commands An integrated device is provided that includes a non-volatile memory having an addressing parallelism and a data parallelism, and a communication interface for interfacing the memory with an external bus. The external bus has a transfer parallelism lower than the addressing parallelism and the data parallelism. The communication interface includes ... ### FreshPatents.com Support |