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Electrical Computers And Digital Data Processing Systems: Input/output > Intrasystem Connection (e.g., Bus And Bus Transaction Processing) > Bus Interface Architecture > Path Selecting Switch Path Selecting SwitchPath Selecting Switch patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236017 - Synchronizing primary and secondary fabric managers in a switch fabric The present disclosure includes systems and techniques relating to interconnecting components within computing and network devices. In general, in one implementation, the technique includes: sending a message from a primary fabric manager to an initiating secondary fabric manager in a switch fabric; obtaining, at the secondary fabric manager and in ... 10/12/06 - 20060230220 - Fibre channel switch system, information processing system, and login procedure Provided is a fibre channel switch system to which a server and a storage system are connected. The fibre channel switch system includes: a host controller for controlling a fibre channel protocol, to which the server is connected; a management table for indicating a hardware address of the host controller; ... 10/12/06 - 20060230219 - Virtualization of an i/o adapter port using enablement and activation functions A method is provided for configuring a communication port of a communications interface of an information handling system into a plurality of virtual ports. A first command is issued to obtain information indicating a number of images of virtual ports supportable by the communications interface. A second command is then ... 10/05/06 - 20060224813 - Advanced switching optimal unicast and multicast communication paths based on sls transport protocol An embodiment of the present invention may comprise a method to calculate current bandwidth usage by existing connections in a switching fabric between endpoints in a device, calculate available bandwidth for a new connection, and select a path from the multiple paths based on the bandwidth calculations. Some embodiments may ... 09/28/06 - 20060218336 - Pci-express communications system To be able to transmit a response packet to a target, which is the original request source node, even if, after issuing a request from a node to another, a bus ID/a device ID is replaced in the PCI-Express switch before said another node makes a response to the request ... 09/28/06 - 20060218335 - Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. A bus interconnect is configured to interface the processors to the memory devices. The ... 09/21/06 - 20060212641 - Multi-channel serial advanced technology attachment control system and control card thereof A multi-channel serial advanced technology attachment (SATA) control system and control card thereof includes a first SATA control module, a first access-grant arbitration unit, a second SATA control module, a second access-grant arbitration unit and a path selection module. Through an arbitration process performed in the first and second access-grant ... 09/14/06 - 20060206656 - Apparatus and method for preventing loops in a computer network A network device is configured in a manner to prevent connectivity loops such as one way connectivity loops. A user configures a port of the network device to have an associated state. The state indicates that the port is for communication up the spanning tree towards a root network device, ... 09/07/06 - 20060200614 - Computer system using serial connect bus, and method for interconnecting a plurality of cpu using serial connect bus A computer system enable system operation by hiding the peculiarity of an upstream port of a switch in a computer system in which a plurality of CPU units are interconnected by a PCI Express switch. When a CPU unit, which is connected to the upstream port of a serial connect ... 08/17/06 - 20060184712 - Switch architecture independent of media A network device for handling data and a method for handling data in a network device are disclosed. The network device includes at least one media port and at least one high speed docking station, communicating with the at least one media port. At least one master is provided in ... 08/17/06 - 20060184711 - Switching apparatus and method for providing shared i/o within a load-store fabric An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains (OSDs) ... 08/10/06 - 20060179204 - Method and apparatus for communicating over a resource interconnect A resource interconnect architecture and associated descriptor protocol provides more efficient communication between different resources in a data processing system. One embodiment uses a backdoor interconnect that allows some resources to communicate without using a central resource interconnect. Another embodiment uses nested descriptors that allow operations by different resources to ... 06/22/06 - 20060136651 - Selectively-switchable bus connecting device for chip device A selectively-switchable bus connecting device is proposed, which is designed for use in conjunction with a chip device for connecting the multiple signal lines of the chip device's internal bus in a user-specified mapping manner to the multiple signal lines of a socket on an external circuit board. This feature ... 06/08/06 - 20060123182 - Distributed kvm and peripheral switch The present invention relates to a system and method for switching keyboard and mouse devices and video displays, as well as USB peripheral devices, between USB hosts and video sources over extended distances. Provided is a distributed KVM and peripheral switch where a USB keyboard and mouse is emulated to ... 05/18/06 - 20060106968 - Intelligent platform management bus switch system A method according to one embodiment may include routing information between a plurality of Intelligent Platform Management (IPM) controllers utilizing an intelligent platform management bus (IPMB) switch system. The IPMB switch system may comprise a first and second IPMB switch. The first IPMB switch may be coupled to each of ... 05/04/06 - 20060095645 - Multi-function chipset and related method Multi-function chipset and related design/manufacturing method for realizing different kinds of chipsets respectively supporting accelerated graphic port (AGP) bus and peripheral component interconnect extended (PCI-X) bus. The integrated circuit of the chipset includes both the AGP and PCI-X bus controllers, which share a common I/O pad configuration, and the chipset ... 04/27/06 - 20060090027 - Disk array control device with two different internal connection systems A disk array control device which includes a plurality of channel interface (IF) units, a plurality of disk IF units, a cache memory unit, and a shared memory unit. The connection system between the plurality of channel IF units and plurality of disk IF units and the cache memory unit ... 03/30/06 - 20060069842 - Communication mechanism The invention provides an interconnection architecture for semiconductor devices. Cross bar switches are traditionally placed in the center of the IC. However, this location may also be the preferred location for the centralized logic in the IC. This invention, known as a cross bar ring or CBR, provides cross bar ... 02/23/06 - 20060041707 - Computer systems with multiple cpu configuration A method and device providing multiple CPU configuration of a computer system are disclosed. A motherboard supporting the device is also provided. When a module with a first CPU is not connected to the motherboard via an expansion connector, a second CPU is connected with the system logic unit, and ... 02/09/06 - 20060031625 - Hybrid switching architecture A hybrid switching module includes a hybrid switching module processor data channel; a hybrid switching module main data channel; an input/output link data channel; a switch coupled to the hybrid switching module processor data channel; and a bridge coupled to the hybrid switching module main data channel; wherein the switch ... 12/29/05 - 20050289281 - Non-blocking switch fabric A non-blocking switch fabric with data synchronization of ports coupled thereto includes a switching matrix and a plurality of ports coupled to the switching matrix. Each port has an incoming queue, an outgoing queue, a module for generating a sync packet coupled to the outgoing queue and a module for ... 12/29/05 - 20050289280 - Switching fabric bridge A non-blocking switch fabric for bridging peripheral component interconnect extended busses includes a switching matrix and a plurality of ports coupled to the switching matrix. Each port has an incoming queue, an outgoing queue, a first module for generating a packet, the packet including one of a left-aligned command and ... 12/22/05 - 20050283563 - Asynchronous/synchronous kvmp switch for console and peripheral devices A signal switch for sharing a video monitor, a plurality of console devices compliant with an industry standard and one or more than one peripheral device in any of a plurality of computer systems, is provided comprising a CPU with a first memory for storing a management program for managing ... 11/10/05 - 20050251612 - Separating transactions into different virtual channels In one embodiment of the present invention, a method may include separating incoming transactions to an agent of a coherent system into at least a first channel, a second channel, and a third channel, based upon a type of the incoming transactions. The incoming transactions may be sent by a ... 11/10/05 - 20050251611 - Transmitting peer-to-peer transactions through a coherent interface In various embodiments, the present invention includes a method for receiving a transaction having first header information from a first peer device at a first agent of a coherent system, inserting second header information onto the transaction, and routing the transaction to a second peer device using the second header ... 10/20/05 - 20050235092 - High performance computing system and method A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard. ... 10/13/05 - 20050228935 - High speed data bus The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and ... 10/06/05 - 20050223152 - Semiconductor memory device and method of outputting data signals A semiconductor memory device includes first to third data buses, a first connection circuit and a second connection circuit. The first connection circuit is provided between the first data bus and the second data bus, inverts and transfers a first output signal on the first data bus read out from ... 09/29/05 - 20050216650 - Bus system, station for use in a bus system, and bus interface The invention relates to a bus system comprising a first station and a second station coupled by a bus for transferring signals. The bus is arranged to operate according to a protocol in which said first station repeatedly sends requests for data to the second station. The protocol comprises a ... 09/08/05 - 20050198429 - Multilayer system and clock control method The multilayer system includes a multilayer switch which allows simultaneous processing of commands from a plurality of masters. The multilayer switch has a switch master portion corresponding to a master and a switch slave portion corresponding to a slave. The switch master portion outputs to a clock generator a clock ... 07/07/05 - 20050149660 - Multiprocessor data processing system having a data routing mechanism regulated through control communication A data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one implementation, a data processing system includes at least first through third processing units, data storage coupled to the ... 06/30/05 - 20050144351 - Computer accessory device-usb sharer A computer accessory device—USB share is comprised of a multiplexer, which is connected to a computer host; a human interface device (HID) chip, which is connected to one output end of the multiplexer; a device output end, which is connected to another output end of the multiplexer; and a busyness ... 06/23/05 - 20050138261 - Managing transmissions between devices Provided are a method, system, and program for processing a transmission from a first device to a second device. An identification transmission is received including an interface address from the first device. A determination is made as to whether the identification transmission indicates a recognized vendor identifier. An interface address ... ### FreshPatents.com Support |