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Electrical Computers And Digital Data Processing Systems: Input/output > Intrasystem Connection (e.g., Bus And Bus Transaction Processing) > Bus Interface Architecture > Bus Bridge Bus BridgeBus Bridge patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/19/06 - 20060236016 - Method, system, and apparatus to support device configuration A technique is discussed for representing cores and threads of a multi-core processor as a virtual device with a bridge device with the functionality of a PCI bridge device with an ability to direct configuration accesses to a memory image of the virtual device. The bridge device may be incorporated ... 10/05/06 - 20060224811 - Universal safety i/o module A safety control block interfaces to one or more devices utilizing one or more communication protocols wherein a network interface receives and/or transmits data directly from a network. A backplane interface receives and/or transmits data from a backplane. A backplane extension receives and/or transmits data from a backplane. A processing ... 09/21/06 - 20060212639 - Bus segment decoder Disclosed are a system and method of forwarding bus transactions from a source device to a target device in multiple data bus environment. A bridge is coupled between a first data bus and a second data bus while a target device is coupled to the first data bus at a ... 09/21/06 - 20060212638 - Motherboard and control method thereof A motherboard includes a south-bridge chipset, a north-bridge chipset and a central processor unit (CPU). The south-bridge chipset generates at least control-setting data. The north-bridge chipset has a reset register for controlling the north-bridge chipset to generate a reset signal and a control-set resister for storing the control-setting data generated ... 09/14/06 - 20060206651 - Method and apparatus for control of a first device by a data storage device through an ide bus A system includes a first device; an Integrated Drive Electronics (IDE) bus; and a data storage device having a first task file register, the data storage device being coupled to the first device via the IDE bus for storing data within the data storage device as received from the first ... 09/14/06 - 20060206650 - Hub with a host-to-host transmission function For implementing a host-to-host transmission function, a hub comprises an uplink port and a host port for being linked a host respectively, a hub control unit connected to the uplink port, and a bridge connected between the host port and hub control unit for the hosts communicate with each other. ... 08/24/06 - 20060190657 - Bus communication apparatus for programmable logic devices and associated methods A programmable logic device (PLD) includes programmable logic circuitry and a bridge circuitry. The bridge circuitry includes a first interface circuitry and a first signal select circuitry. The first signal select circuitry couples to the first interface circuitry and the programmable logic circuitry. The bridge circuitry further includes an information ... 08/24/06 - 20060190656 - Flexible processing hardware architecture A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and ... 08/24/06 - 20060190655 - Apparatus and method for transaction tag mapping between bus domains An apparatus and method to provide tag mapping between bus domains across a bus bridge. The preferred embodiments provide a simple tag mapping design while maintaining unique IDs for all outstanding transactions for an overall increase in computer system performance. The preferred embodiment is a bus bridge between a GPUL ... 08/17/06 - 20060184707 - Error injection A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but ... 06/08/06 - 20060123178 - Generating multiple traffic classes on a pci express fabric from pci devices A system having a PCI Express fabric and PCI devices connected thereto transmits data from the PCI devices having PCI Express traffic classes assigned. A PCI Express to PCI bridge assigns a predetermined address to the grant line for each PCI device coupled to the PCI bus and stores this ... 06/08/06 - 20060123177 - Method and apparatus for transporting and interoperating transition minimized differential signaling over differential serial communication transmitters A differential serial communication transmitter (i.e. PCI Express or other suitable type of transmitter) can be used to transport and interoperate transition minimized differential signaling. The differential serial communication transmitter control logic receives display configuration control data and in response configures at least one differential serial communication transmitter of a ... 06/01/06 - 20060117126 - Processing unit for efficiently determining a packet's destination in a packet-switched network A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one embodiment, the systolic array pipeline includes a plurality of programmable functional units and register files ... 05/04/06 - 20060095633 - Data transmission coordinating method A data transmission coordinating method is used between a central processing unit and a bridge chip of a computer system. By entering the computer system into a coordinating state, the data transmission coordinating method is executed. The bridge chip and the CPU are informed of maximum bit numbers of each ... 05/04/06 - 20060095632 - Data transmission coordinating method and system In a data transmission coordinating method, information associated with a first transmission standard of the bridge chip is read from a memory unit of the computer system. A first signal from the bridge chip is issued to the central processing unit to inform the central processing unit of the first ... 05/04/06 - 20060095631 - Data transmission coordinating method In a data transmission coordinating method, the computer system enters a coordinating state, and a first signal is issued from the central processing unit to the data transmission standard storage unit of the bridge chip. In response to the first signal, a second signal is issued from the data transmission ... 04/20/06 - 20060085586 - Voltage indicator signal generation system and method The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received system reset signal, to ... 04/20/06 - 20060085585 - Main board with a slot-sharing circuit for pci express x16 and x1 slot to be connected to A main board has a slot-sharing circuit for a PCI express ×16 slot and a PCI express ×1 slot to be electrically connected to, an ×16 resistor-capacitor circuit corresponding to the PCI express ×16 slot, an ×1 resistor-capacitor circuit corresponding to the PCI express ×1 slot, a slot installed on ... 04/13/06 - 20060080489 - Bus bridge and data transfer method In response to a direct memory access (DMA) request, a direct memory access controller (DMAC) performs reading at a host side at which a high-speed bus master is arranged. A bus bridge sends a dummy data to the DMAC, and performs reading at an input/output (I/O) side at which a ... 02/23/06 - 20060041703 - Computer systems with multiple system configurations A module with a first Northbridge area comprising a first CPU, a first system memory, a first accelerated graphics port and a first Northbridge is provided. A motherboard with a Southbridge and a second Northbridge area comprising a second CPU, a second system memory, a second accelerated graphics port and ... 02/23/06 - 20060041702 - Controller apparatus and method for improved data transfer Embodiments of the invention include a controller apparatus, system and method for transferring data between data storage devices within a computer system. The inventive controller apparatus includes device interface logic for connecting the controller to a plurality of data storage devices, e.g., a hard disk device and a CD-RW device, ... 02/23/06 - 20060041701 - Method and device for adjusting lane ordering of peripheral component interconnect express A method for adjusting the PCI Express lane ordering is disclosed, comprising the following steps. The first packet associated with a first PCI Express lane ordering is sent to the peripheral device. The peripheral device replies the second packet associated with the second PCI Express lane ordering. Whether the PCI ... 02/16/06 - 20060036796 - Method and apparatus for setting a primary port on a pci bridge An apparatus and a method for setting a primary port on a PCI multi-port bridge. More specifically, there is provided a method that comprises detecting a configuration signal at the PCI multi-port bridge and automatically setting the primary port on the PCI multi-port bridge based on the configuration signal. A ... 02/02/06 - 20060026328 - Apparatus and related method for calculating parity of redundant array of disks For error tolerance in a redundant array disks (RAID), a parity data is calculated according to plurality of data respectively accessed in disks of the RAID. A hardware calculation module for parity calculation can be implemented in a RAID controller. With direct memory access (DMA) capability of the RAID controller, ... 02/02/06 - 20060026327 - Isolation of input/output adapter traffic class/virtual channel and input/output ordering domains Method, apparatus and system for controlling input/output adapter data flow operations in a data processing system that includes at least one of a traffic class mechanism in conjunction with virtual channel resources so as to be able to associate Load/Store and DMA flows to/from an input/output adapter, and a relaxed ... 01/19/06 - 20060015671 - Distributed peer-to-peer communication for interconnect busses of a computer system There is provided a distributed peer-to-peer communication system for interconnect busses of a computer system. More specifically, there is provided a method comprising transmitting a request to establish an isochronous channel between a first device and a second device, establishing the isochronous channel between the first device and the second ... 01/12/06 - 20060010278 - System and method for managing bus numbering Bus numbering management for an information handling system, such as a personal computer, is provided by interfacing one or more selectively hidden devices with one or more buses through either a hardware or software implementation. If an inactive bus becomes active, then disabling of a selectively hidden device interfaced with ... 12/29/05 - 20050289277 - Data processing on extended mobile access enabled computer Embodiments of the present invention can make data from a primary system of a computer available to an extended mobile access module embedded in the computer. ... 12/08/05 - 20050273542 - Configurable communication template for designing and implementing an accelerator A system and method of designing an accelerator for a processor-based system. The accelerator design problem is partitioned into a data communicate module design problem and a data compute core module design problem. The hardware design of the data communicate module is achieved through a predetermined communication template which is ... 11/17/05 - 20050256990 - Integrated circuit having processor and bridging capabilities An apparatus according to one embodiment may include an integrated circuit. The integrated circuit may include a processor, a bridge, and circuitry capable of coupling the bridge and the processor to a first bus and to a second bus. The first bus may be compatible with a first bus protocol, ... 11/17/05 - 20050256989 - Method of vme module transfer speed auto-negotiation In a multi-service platform system (103), a method of transfer speed (119) negotiation includes an initiator VME module (402) communicating a negotiation code (406) to a responder VME module (404) using a two edge source synchronous protocol. If the responder VME module recognizes the negotiation code, the responder VME module ... 11/03/05 - 20050246475 - Method and apparatus for constructing wired-and bus systems A large multimaster I2C bus system is partitioned into smaller bus segments. The bus segments are connected by bridges that isolate the segments and direct selected transactions and commands between the segments. By programming address bitmaps that are internal to each bridge, transactions can pass through the bridges so that ... 11/03/05 - 20050246474 - Monolithic vmebus backplane having vme bridge module A computer system (300) includes a monolithic VMEbus backplane (304) and a VME bridge module (302) integrally embedded in the VMEbus backplane. The VME bridge module segments the monolithic VMEbus backplane into the plurality of VME backplane segments. ... 11/03/05 - 20050246473 - Method for programming firmware hubs using service processors A method and system that enables a service processor to program a system resource. The service processor uses a JTAG Bus to request a system processor to enter into probe mode. Once in probe mode, the service processor sends a signal with instructions to the system processor. Upon execution of ... 10/27/05 - 20050240706 - Peripheral device control system A peripheral device control system comprises a processor, a first bus, and a bridge device. The processor comprises a set of control instructions. The first bus couples to the processor by the first bus protocol. The bridge device communicates with the first bus by the first bus protocol and communicates ... 10/13/05 - 20050228930 - Programmable inter-virtual channel and intra-virtual channel instructions issuing rules for an i/o bus of a system-on-a-chip processor A method and apparatus for programming instruction issuing rules for instructions residing among various virtual channels, as well as the same virtual channel of an I/O bus interface for a system-on-a-chip processor. In the method and apparatus of the present invention both intra-virtual channel dependencies and inter-virtual channel dependencies are ... 10/13/05 - 20050228929 - Bridge circuit A bridge circuit and method of transferring data is disclosed. The bridge circuit comprises a first interface circuit operable to receive data from a data source at a first data rate; a second interface circuit operable to transmit said data to a data receiver at a second data rate; a ... 09/29/05 - 20050216640 - Processor bus arrangement A processor bus arrangement including several data processing units, each connected to a line system specified as a bus. The bus includes connection units and bus segments, where the bus segments are connected to the bus in a seperable manner through the connection units. This guarantees that the functional units, ... 09/08/05 - 20050198427 - Portable electronic system and accessing method thereof A portable electronic device equipped with multi-function high speed bus and the relevant method is provided in the invention. The portable electronic device includes a main electronic apparatus for connecting to an expansion device through an expansion pack. The central processing unit (CPU) of the main electronic apparatus is connected ... 08/25/05 - 20050188143 - Methods and circuits for stacking bus architecture A system for connecting multiple repeaters into a single collision domain comprising a first repeater, a second repeater and a stacking bus. The first repeater has a plurality of network ports. The second repeater also has a plurality of network ports. The stacking bus connects the first repeater and the ... 08/04/05 - 20050172063 - Scalable bus structure A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be configured to broadcast on the first channel read and write address information, read and write control signals, and ... 07/28/05 - 20050165996 - Method and apparatus for driving multiple peripherals with different clock frequencies in an integrated circuit The invention is a system for selecting a peripheral, the peripheral receiving a first clock frequency. The invention comprises the following. A processing circuit receives a second clock frequency, where the first and second clock frequencies are different. The processing circuit is configured to transmit a select signal. A bridge ... 06/30/05 - 20050144350 - Noise attenuating bus structure and method for a mobile communication A bus structure of a mobile communication terminal for reducing digital noise is disclosed. The bus structure comprises a bus switch controller, a first element having a first bus, a second element having a second bus, and a common bus for connecting the first bus and the second bus. A ... 06/23/05 - 20050138260 - On-chip bus This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting the multiple outstanding transactions with a plurality of on-chip devices over ... 06/09/05 - 20050125588 - Semiconductor integrated circuit A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the bus line, and a control circuit which is formed at the peripheral circuits. The control circuit receives a select signal and controls ... 06/09/05 - 20050125587 - Semiconductor integrated circuit A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the busline, and a control circuit which is formed at the peripheral circuits. The control circuit receives a select signal and controls the ... 06/09/05 - 20050125586 - Alternate non-volatile memory for robust i/o The present invention relates to a method, circuit, and system for performing write journal operations on a bus interface controller board or bus interface controller integrated circuit chip. This is achieved by placed a write journal memory on the board or chip and supplying power to it from an external ... 06/02/05 - 20050120156 - Semiconductor integrated circuit A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the busline, and a control circuit which is formed at the peripheral circuits. The control circuit receives a select signal and controls the ... ### FreshPatents.com Support |