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Electrical Computers And Digital Data Processing Systems: Input/output > Interrupt Processing > Handling Vector Handling VectorHandling Vector patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.06/08/06 - 20060123172 - Trap mode register Systems, methodologies, media, and other embodiments associated with a system configured with a trap mode register, multiple interrupt vector address registers, and multiple interrupt vector tables are described. One exemplary system embodiment includes a logic for initializing the trap mode register, for initializing interrupt vector address registers, and for initializing ... 06/08/06 - 20060123171 - Method and apparatus for using address traps to pace writes to peripheral devices A system and method for pacing writes to a legacy peripheral device includes a control block configured to trap on the address of the legacy peripheral device and slows the rate that the CPU posts writes to avoid backpressure. ... 01/19/06 - 20060015668 - Message signaled interrupt redirection table In some embodiments, the inventions include a chip having a message signaled interrupt redirection table (MRT) that contains entries including an address field and a data field. The chip also includes translation circuitry to translate an address field and a data field of a message signaled interrupt (MSI) signal by ... 10/13/05 - 20050228923 - Efficiently supporting interrupts A method, system, and article of manufacture to efficiently support interrupts of a computer system. A message-based interrupt from a device of the computer system is intercepted. A fake line-based interrupt for the device corresponding to the message-based interrupt is determined, wherein an operating system (OS) of the computer system ... 07/21/05 - 20050160210 - Vectored interrupt control within a system having a secure domain and a non-secure domain There is provided an apparatus for processing data, said apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including: at least one secure mode being a mode in said secure domain; and at least one non-secure mode being a mode ... ### FreshPatents.com Support |