REGISTER now for FREE 
|
FREE patent keyword monitoring and additional FREE benefits. REGISTER now for FREE
|
|
|
Electrical Computers And Digital Data Processing Systems: Input/output > Interrupt Processing Interrupt ProcessingInterrupt Processing patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/12/06 - 20060230208 - System and method for presenting interrupts An information processing system is provided which includes an interrupt table including a plurality of entries relating to interrupts requested by entries in a plurality of event queues. The entries of the interrupt table reference identifiers, and the identifiers are assigned to events from a pool of identifiers in accordance ... 09/28/06 - 20060218328 - Systems and methods for an augmented interrupt controller and synthetic interrupt sources Various embodiments of the present invention are directed to augmented interrupt controllers (AICs) and to synthetic interrupt sources (SISS) providing richer interrupt information (or “synthetic interrupts” or “SIs”). The AIC and SIS provide efficient means for sending and receiving interrupts, and particularly interrupts sent to and received by virtual machines. ... 09/21/06 - 20060212633 - Method and system of routing network-based data using frame address notification A method and system for routing network-based data arranged in frames is disclosed. A host processor analyzes transferred bursts of data and initiates an address and look up algorithm for dispatching the frame to a desired destination. A shared system memory existing between a network device, e.g., an HDLC controller, ... 09/14/06 - 20060206646 - Microcontroller with an interrupt structure having programmable priority levels with each priority level associated with a different register set Typically, for processing systems it must be guaranteed that all interrupted program stream parameters are restored before the execution of the first program stream resumes. If during this transfer an interrupt occurs, then all data may not be stored or restored. If the error free storage of the program register ... 08/31/06 - 20060195645 - Interface for prototyping integrated systems An interface is described which has at least one chip side port with a first plurality of pins for conveying fields of a packet and first and second circuit side ports each port having a set of pins with a lower number than the first set of pins in the ... 08/31/06 - 20060195644 - Interrupt mechanism on an io adapter that supports virtualization A mechanism for handling event notifications or interrupts in a logically partitioned computing system having IO adapters that support adapter virtualization are provided. A virtual adapter associated with a physical IO adapter detects an event, identifies a logical partition associated with the event, and writes an event notification entry in ... 08/10/06 - 20060179198 - Micro interrupt handler A system and method is provided for improved interrupt handling via a micro interrupt handler. Upon an interrupt signal being sent to a processor running a task, a first part of the running task is stored to system memory via direct memory access. A micro interrupt handler is read from ... 07/27/06 - 20060168385 - Interrupt controller for a microprocessor An interrupt controller for a microprocessor having a plurality of event memories which are combined to form at least one group and each having an input for a setting signal and an output for an event memory signal which portrays the state of the event memory. The setting signal for ... 07/27/06 - 20060168384 - Maximal length packets Detecting and flushing maximal length packets is set forth herein. In one embodiment, the method comprises receiving a flushing event and, in response to the flushing event, repeatedly detecting a maximum length packet of write data from a write combining storage area and flushing the detected maximum length packet to ... 07/13/06 - 20060155907 - Multiprocessor system A multiprocessor system from which redundancy relating to data assurance at the time of data communication between processing sections is removed. At the time of data communication between a network processing section (101) and a real-time processing section (201), exclusive control of a shared memory is performed by means of ... 07/06/06 - 20060149877 - Interrupt management for digital media processor A method includes receiving a first interrupt from a digital media processor and blocking execution of an application program while the first interrupt is being handled. The method further includes receiving a second interrupt from the digital media processor and allowing execution of the application program to continue while the ... 06/29/06 - 20060143351 - Method, apparatus and system to generate an interrupt by monitoring an external interface In some embodiments, a method, apparatus and system to generate an interrupt by monitoring an external interface are presented. In this regard, an interrupt agent is introduced to communicate over a serial interface with an input/output (I/O) extender and to save a relevant status of the I/O extender in a ... 06/22/06 - 20060136641 - Context save method, information processor and interrupt generator A context save method, an information processor and an interrupt generator for restoring, after a reset of a CPU, CPU context information such as the interrupt acceptance state of the CPU before the CPU reset. An interrupt controller stores CPU context information set in a CPU in a memory before ... 06/22/06 - 20060136640 - Apparatus and method for hardware semaphore A device and method for hardware semaphore is provided to be used in a multi-processor system. The device for hardware semaphore comprises a plurality of semaphores, a semaphore module register set, a control logic unit, a bus interface unit, and an interrupt generation unit. According to the invention, a single ... 06/08/06 - 20060123170 - Systems for generating synchronized events and images A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system is provided. In a sender-receiver dichotomy, one node is deemed the sender and the others act as receivers. The sender determines trigger values for each of the nodes in ... 05/11/06 - 20060101180 - Multiprocessor system comprising an observation element The invention relates to a multiprocessor system, which comprises memory elements, input/output units and a central bus system, whereby the input/output units access the memory elements via the central bus system, using direct memory access. Said system is equipped with a bus observation element, which during the read/write access by ... 05/04/06 - 20060095624 - Retargeting device interrupt destinations Provided are a method, system, and article of manufacture, where a determination is made of one of a plurality of processors to disable, where the plurality of processors are processing interrupts from at least one device. An interrupt directed at the determined processor is communicated to at least one other ... 05/04/06 - 20060095623 - Digital interface receiver apparatus An audio controlling device generates an audio mute signal based on the level of a power-supply voltage supplied from the source equipment, whether a clock signal has been input or not, whether a digital signal has been input or not, whether a multiplier circuit is being locked or not, an ... 04/20/06 - 20060085582 - Multiprocessor system An interrupt notification network is provided for a multiprocessor system in which many processor units are installed. An interrupt notification source processor unit transmits an interrupt notification packet to an interrupt notification destination processor unit. The interrupt notification packet to be transmitted by the interrupt notification source processor unit contains ... 04/20/06 - 20060085581 - Computer system and method for inhibiting interruption of a user that is actively using the computer system A computer system and method inhibit interruption of a user that is actively using the computer system. A user is actively using the computer system if the user has provided defined input within a time period specified in a “do not disturb” specification. For example, if the time period in ... 04/20/06 - 20060085580 - Method for synchronizing processors in smi following a memory hot plug event A method for synchronizing processors during a system management interrupt caused from a memory hot plug event in multiple processor systems is disclosed. In one embodiment, a method for synchronizing processors during an assertion of a system management interrupt (SMI) in an information handling system including, for each processor, identifying ... 04/06/06 - 20060075172 - Method for applying interrupt coalescing to incoming messages based on message length A balanced approach is provided for interrupt coalescing, wherein interrupts of locking and other small size packets are maximized, while large data segment interrupts are minimized. Thus, the most desirable interrupt characteristics of both large data segments and smaller packets are achieved. Usefully, a data processing system has an adapter ... 04/06/06 - 20060075171 - Providing unique event notifications Embodiments of the present invention pertain to methods and apparatuses for providing unique event notifications is described. In one embodiment, an object accessor accesses an object that represents hardware. A notification value accessor acceses a notification value. A universally unique identifier (UUID) accessor accesses a UUID, and a unique action ... 03/30/06 - 20060069833 - Batch processing of interrupts A computer-implemented method for handling pending interrupt vectors of a pending interrupt list is disclosed. The method includes batch-reading the set of pending interrupt vectors into a working list of working interrupt vectors. The method also includes performing interrupt handling of the working interrupt vectors using an interrupt handling arrangement ... 03/23/06 - 20060064529 - Method and system for controlling peripheral adapter interrupt frequency by transferring processor load information to the peripheral adapter A method and system for controlling interrupt frequency by transferring processor load information to a peripheral adapter provides adaptive interrupt latency to improve performance in a processing system. A device driver obtains current processor load information from an operating system or directly from processor usage counters. The estimated processor load ... 03/23/06 - 20060064528 - Privileged resource access At least one entry in an original interrupt vector table is replaced with an instruction set to handle access to a privileged resource. An operating system privilege level is modified to one or more resources. Subsequent access to the privileged resource causes an interrupt. Processing of the interrupt is directed ... 03/16/06 - 20060059286 - Multi-core debugger In a multi-core processor, a high-speed interrupt-signal interconnect allows more than one of the processors to be interrupted at substantially the same time. For example, a global signal interconnect is coupled to each of the multiple processors, each processor being configured to selectively provide an interrupt signal, or pulse thereon. ... 03/02/06 - 20060047877 - Message based interrupt table An interrupt processing technique is provided where an interrupt message is sent to an interrupt controller of a processor in response to an interrupt request from an individual device. The interrupt message comprises a memory address and interrupt status information. The memory address is specifically allocated to the device that ... 03/02/06 - 20060047876 - System and method for processing system management interrupts in a multiple processor system A system and method for processing system management interrupts in multiple processor systems is disclosed. In one embodiment, a method for processing a system management interrupt (SMI) in an information handling system including, for each processor, identifying whether the processor is an interrupt handling processor assigned to perform processing tasks ... 03/02/06 - 20060047875 - System and method for message delivery across a plurality of processors A system and method is provided to deliver messages to processors operating in a multi-processing environment. In a multi-processor environment, interrupts are managed by storing events in a queue that correspond to a particular support processor. A main processor decodes an interrupt and determines which support processor generated the interrupt. ... 02/16/06 - 20060036791 - Chipset support for managing hardware interrupts in a virtual machine system In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a distinct interrupt request line. Each multiplex block is to ... 02/02/06 - 20060026323 - Information processing apparatus and smi processing method thereof An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a multifunctional device having a plurality of functions each potentially causing an SMI; and a plurality of signal lines provided between the controller and ... 02/02/06 - 20060026322 - Interrupt management in dual core processors A system comprising an interrupt logic comprising a data structure and adapted to process a plurality of interrupt requests, and a plurality of processor cores coupled to the interrupt logic. The data structure comprises a plurality of entries, each entry corresponding to a different interrupt request and having multiple fields. ... 02/02/06 - 20060026321 - Increasing the number of i/o decode ranges using smi traps A method of increasing the quantity of input/output (I/O) decode ranges using system management interrupts (SMI) traps is disclosed. In one aspect, the present disclosure teaches a method of increasing the quantity of I/O decode ranges using SMI traps in a chipset including generating a system management interrupt (SMI) based ... 01/26/06 - 20060020730 - Single bios technique for supporting processors with and without 64-bit extensions A technique according to the invention enables a single BIOS to support processors with or without 64-bit extensions efficiently. The BIOS creates a data structure having entries that correspond to elements stored in a state save area. The state save area elements themselves may be located at different addresses depending ... 12/29/05 - 20050289273 - Communication apparatus using inter integrated circuit bus and communication method thereof A communication apparatus that communicates with an external apparatus using an I2C bus, the communication apparatus having a microprocessor to process data received in response to an interrupt activation signal, a first reception unit to receive data transmitted from the external apparatus through the I2C bus and temporarily store the ... 12/29/05 - 20050289272 - Method and equipment for verifying propriety of system management policies to be used in a computer system A policy verification method in an information processing system for verifying whether the policy rule operates correctly. The method verifies the policy in an information processing system including at least one component, using policies describing a series of system management operations to be performed when an event occurs, and automatically ... 12/29/05 - 20050289271 - Circuitry to selectively produce msi signals In some embodiments, the inventions include a chip having a status register circuit coupled to conductors to receive interrupt event signals to provide source signals corresponding to the interrupt event signals. The chip also includes a control register circuit to provide source enable signals for selective ones of the interrupt ... 12/22/05 - 20050283556 - Transfer of waiting interrupts Apparatus and methods are provided for transferring interrupts. One embodiment of a computing device includes a first processor, a memory in communication with the first processor, and computer executable instructions stored in memory and executable on the first processor. The computer executable instructions are provided to select an interrupt, that ... 12/22/05 - 20050283555 - Computer system and method for transmitting interrupt messages through a parallel communication bus A computer system and a method for transmitting interrupt messages through a parallel communication bus are provided. The computer system includes a first device operably communicating with a second device via a parallel communication bus. The first device is configured to transmit a first interrupt message through the parallel communication ... 12/22/05 - 20050283554 - Computer system and method for queuing interrupt messages in a device coupled to a parallel communication bus A computer system and a method for queuing interrupt messages are provided. The computer system includes a parallel communication bus and a first device operably coupled to the parallel communication bus. The first device is configured to receive first and second interrupt messages transmitted through the parallel communication bus to ... 12/08/05 - 20050273540 - Interrupt handling system The invention provides an interrupt handling system to process a generated interrupt. At least one input is arranged to provide a predetermined active level, with a detection circuit associated with the input which is selectively configurable to detect either the active level or an inactive level. An interrupt request message ... 12/01/05 - 20050268016 - Method and apparatus for dynamic suppression of spurious interrupts An apparatus and method for dynamic suppression of spurious interrupts in a computer system. More specifically, there is provided a method that comprises providing a look-up table comprising source IDs and corresponding time delays for each of a plurality of interrupt lines, monitoring each of the plurality of interrupt lines, ... 11/24/05 - 20050262282 - Interrupt sharing method for edge triggering An interrupt sharing method for edge triggering is disclosed. First, interrupt requests of various devices are detected before entering a main interrupt process. Various device interrupt sub-routines are called in order to process device interrupts. Finally, the device interrupt sub-routines are called in order again according to the interrupt processing ... 11/10/05 - 20050251605 - Apparatus and method for communications between agents in pci system The present invention discloses a method for sending data from a second agent to a first agent in a bus system having a host and at least two agents of the first agent and at least one second agent. The first and second agents are connected by an interrupt signal ... 11/03/05 - 20050246466 - Method and system for detecting excessive interrupt processing for a processor A method and system is provided for detecting excessive interrupt processing for a processor. The method includes the operation of defining an interrupt processing period during which measuring of interrupts for a processor takes place. The amounts of time being spent by the processor in an interrupt context can then ... 11/03/05 - 20050246465 - Method and system for maintaining a desired service level for a processor receiving excessive interrupts A method and system for maintaining a desired service level for a processor receiving excessive interrupts. The method includes the operation of defining an interrupt processing period during which interrupts will be measured for a processor. The amounts of time spent by the processor during the interrupt processing period in ... 10/27/05 - 20050240701 - Interrupt control apparatus Apparatus for controlling multiple interrupts comprises units for: pre-storing, for each interrupt cause, information identifying an interrupt processing program executed in response to occurrence of the interrupt cause and level information indicating the interrupt processing program level; comparing, upon occurrence of an interrupt cause, execution levels indicated by the level ... 10/27/05 - 20050240700 - Method and apparatus for facilitating recognition of an open event window during operation of guest software in a virtual machine environment In one embodiment, a method includes transitioning control to a virtual machine (VM) upon receiving a request from a virtual machine monitor (VMM), determining that the request to transition control is associated with a request to be informed of an open event window, performing an event window check to determine ... 10/13/05 - 20050228919 - System, method and device for real time control of processor A method and device of synchronizing interrupts of a processor with, for example, signals from a synchronization unit such as, for example, a slot timer. In advance of the start of a slot as may, for example, be indicated by a signal from, for example, a slot timer, a state ... 10/13/05 - 20050228918 - Method and apparatus for supporting interrupt devices configured for a particular architecture on a different platform Method and apparatus for supporting interrupt devices configured for a specific architecture (e.g., APIC-based software and hardware) on a different platform (e.g., a PowerPC platform). One embodiment provides an apparatus for passing interrupts from one or more devices configured for a specific interrupt architecture to one or more processors not ... 10/06/05 - 20050223148 - Electronic apparatus that communicates with host through serial communication interface A smart card that communicates with a host through a serial communication interface at variable transmission speed is provided, where the smart card variably controls the generation of a connection information signal in accordance with data transmission speed information received from the host to transmit the connection information signal to ... 09/29/05 - 20050216635 - Interrupt request program and microcomputer An interrupt controller specifies and outputs the most highly prioritized one of a plurality of interrupt signal requested for output. A CPU executes a process corresponding to an interrupt signal from the interrupt controller and executes OS-provided programs. Based on reception of a request to execute a task level process, ... 09/29/05 - 20050216634 - Method for remote control of computer system A method for remote control of a computer system is disclosed. By pressing buttons of a remote controller, a computer system in remote end is operated. When users in remote end press buttons for transmitting signals, a receiving unit of the computer system receives the signals. Then the receiving unit ... 09/29/05 - 20050216633 - Techniques to manage critical region interrupts Briefly, techniques to manage interrupts and swaps of threads operating in critical region. ... 09/22/05 - 20050210173 - Adapter unit having a handle grip for a personal digital assistant The present invention relates generally to an adapter unit for a personal digital assistant. More specifically, this invention relates to an adapter unit that has a handle grip. The adapter unit provides additional functionality, and improved ergonomics and increased ruggedness to the personal digital assistant. ... 09/08/05 - 20050198422 - Data communication mechanism A data processing apparatus comprises at least one source processor core (110), at least one destination processor core (120), a message handler (130) and a bus arrangement (150) providing a data communication path between the source core, the destination core and the message handler. The message handler (130) has plurality ... 09/08/05 - 20050198421 - Method to execute acpi asl code after trapping on an i/o or memory access Embodiments may include an interrupt handling system to generate software level interrupts in place of hardware level interrupts. The interrupt handling system may invoke an advanced configuration and power management interface (ACPI) and ACPI source language infrastructure, which provides for an SCI independent mechanism for invoking ACPI ASL code. The ... 09/01/05 - 20050193157 - Apparatus and method for interrupt source signal allocation An apparatus and method for interrupt source signal allocation is provided. An interrupt controller may include an interrupt source allocation unit, an interrupt pending register, a control register, a priority register, and/or an interrupt request signal generator. The interrupt source allocation unit may output one or more interrupt source signals ... 09/01/05 - 20050193156 - Data processing system This invention provides a data processing system capable of performing an interrupt exception handling routine as many times as the number of times of occurrence of a request event for the same interrupt exception handling routine if the request event occurs a plurality of times. A software interrupt counter or ... 08/25/05 - 20050188140 - Condition management callback system and method of operation thereof A condition management callback system and method for use with a processor employing a hierarchical register consolidation structure. In one embodiment, the system includes: (1) a condition management structure, (2) a callback abstraction subsystem configured to register a callback for at least one element object in the condition management structure ... 08/18/05 - 20050182879 - Method and apparatus for controlling interrupt storms An apparatus and method for detecting and controlling interrupt storms in a computer system. More specifically, there is provided a method that comprises detecting whether or not a device is producing an interrupt storm, and if the device is producing an interrupt storm, disabling the interrupt being generated by the ... 08/11/05 - 20050177667 - Interrupt priority control within a nested interrupt system A data processing system 2 having a nested interrupt controller 24 supports nested active interrupts. The priority levels associated with different interrupts are alterable (possibly programmable) whilst the system is running. In order to prevent problems associated with priority inversions within nested interrupts, the nested interrupt controller when considering whether ... 07/28/05 - 20050165990 - Interrupt control device The interrupt control device is a Large Scale Integration (LSI) to which a wide variety of other devices, such as macros, can be connected. The interrupt control device includes a plurality of interrupt controllers that executes interrupt processing; a receiving unit that receives an interrupt signal from any one of ... 07/28/05 - 20050165989 - I2c communication system and method enabling bi-directional communications A communication system and method enabling bi-directional I2C communications is disclosed. In the communication system having a master and at least one slave that communicate with each other through an I2C bus comprising a Serial Clock line (SCL) and a Serial Data line (SDA), the master and slave are directly ... 07/14/05 - 20050154813 - Method and apparatus for counting interrupts by type A method, apparatus, and computer instructions for counting interrupts by type. An interrupt count is incremented when a particular type of interrupt occurs. The count may be stored in the IDT or an interrupt count table outside the IDT. The interrupt unit increments the count each time a particular type ... 07/14/05 - 20050154812 - Method and apparatus for providing pre and post handlers for recording events A method, apparatus, and computer instructions for providing pre and post handlers to log trace records before entering or after exiting the interrupt handler. A trace record includes a ‘from’ address where the interrupt occurs or where the branch instruction is executed or a ‘to’ address for the branch to ... 07/14/05 - 20050154811 - Method and apparatus for qualifying collection of performance monitoring events by types of interrupt when interrupt occurs A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring unit (PMU) is used to program hardware counters that collect events associated with a type of interrupt, including nested interrupts. The performance ... 06/30/05 - 20050144348 - System and method for interrupt abstraction A system and method that abstracts an interrupt from a group of interrupts, which may occur in a module, to call another module. Abstracting one interrupt from a group of interrupts allows the called module to deal with only one interrupt. The choice of the interrupt may be based on ... 06/30/05 - 20050144347 - Apparatus and method for interrupt control The interrupt control apparatus in the present invention includes an interrupt vector register for holding address information corresponding respectively to interrupt resources of first type which are managed by an operating system and interrupt resources of second type which are not managed by the operating system, from among the interrupt ... 06/30/05 - 20050144346 - Message based transport mechanism for level sensitive interrupts An interrupt handling technique is provided that may allow for sharing level sensitive interrupts in systems where interrupts are message based, i.e., edge triggered. An interrupt input unit is provided for receiving level sensitive interrupt requests and generating request occurrence signals therefrom. An edge detection unit generates start signals for ... 06/23/05 - 20050138256 - Method and apparatus for processing hot key input using operating system visible interrupt handling Embodiments include an interrupt handling system to generate an operating system visible interrupt such as a message signaled interrupt or interprocessor interrupt by an advanced configuration and power management interface (ACPI) and ACPI source language infrastructure. The interrupt handling system may be used to service hot keys. This interrupt handling ... 06/23/05 - 20050138255 - Method and apparatus for reducing interrupt latency by dynamic buffer sizing A method for reducing interrupt latency in a data processing system wherein a storage device is provided having a predetermined maximum number of storage locations. Data execution circuitry is coupled to the storage device for providing data to the storage device and storing the data in the storage device. Interrupt ... 06/09/05 - 20050125583 - Detecting method for pci system A detecting method for PCI system is provided for accurately detecting the PCI system bugs rapidly. The PCI system comprises a central process unit, a basic input/output system (BIOS), a PCI controller chipset, a PCI bus and at least one PCI device. The detecting method comprises mainly the following steps: ... 06/09/05 - 20050125582 - Methods and apparatus to dispatch interrupts in multi-processor systems Methods and apparatus to dispatch interrupt requests in multi-processor systems are disclosed. In an example method, an interrupt weighted average (IWA) of each of a plurality of processors is generated based on interrupt dispatch information associated with the plurality of processors. Based on the IWA of each of the plurality ... 06/02/05 - 20050120154 - Interruption control system and method An interruption control system includes an interruption message generator, a stop clock control module and an interruption status indicating path. The interruption message generator is used for decoding and identifying a message signaled interrupt (MSI) issued by a first peripheral device or a second peripheral device when interruption is to ... ### FreshPatents.com Support |